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integrated circuits cl rc632 multiple protocol contactless reader ic may 2003 product specification revision 3.0 confidential p h i l i ps semiconductors & i ? code
philips semiconductors product s pecification rev. 3.0; may 2003 multiple protocol contactless reader ic cl rc632 2 confidential contents 1 general info rmation ............................................................................................................ ......7 1.1 scope .......................................................................................................................... ..........................7 1.2 general de scription............................................................................................................ ...................7 1.3 features ....................................................................................................................... .........................8 1.4 ordering in format ion ........................................................................................................... ..................8 2 block di agram .................................................................................................................. .............9 3 pinning info rmation ............................................................................................................ .......10 3.1 pin config uration.............................................................................................................. ...................10 3.2 pin descr iption ................................................................................................................ ....................11 4 digital in terface .............................................................................................................. ..........13 4.1 overview of supported - processor in terfaces ..................................................................................1 3 4.2 automatic -processor inte rface type de tection ...............................................................................13 4.3 connection to different -proces sor types ...................................................................................... ..14 4.3.1 separated read/wr ite strobe .................................................................................................... .........14 4.3.2 common read/wr ite strobe ....................................................................................................... ........15 4.3.3 common read/write strobe and ha nd-shake mechan ism: epp ......................................................16 4.4 spi compatible interface ....................................................................................................... ..............17 5 cl rc632 re gister set .......................................................................................................... ......20 5.1 cl rc632 regist ers overview .................................................................................................... .......20 5.1.1 register bi t behaviour......................................................................................................... ................22 5.2 register de scription ........................................................................................................... .................23 5.2.1 page 0: command and status ..................................................................................................... .......23 5.2.2 page 1: contro l and status ..................................................................................................... ............31 5.2.3 page 2: transmitte r and c ontrol ................................................................................................ .........38 5.2.4 page 3: receiver and decoder c ontrol ........................................................................................... ...44 5.2.5 page 4: rf-timing and channel red undancy ...................................................................................51 5.2.6 page 5: fifo, timer and irq- pin confi guration ...............................................................................58 5.2.7 page 6: rfu.................................................................................................................... ....................63 5.2.8 page 7: test control ........................................................................................................... ................64 5.3 cl rc632 register flags overview ............................................................................................... ....68 5.4 modes of regist er addressing ................................................................................................... .........72 5.4.1 paging me chanism............................................................................................................... ...............72 5.4.2 dedicated address bus.......................................................................................................... .............72 5.4.3 multiplexed a ddress bus........................................................................................................ .............72 6 memory organisation of the e2prom .................................................................................73 6.1 diagram of the e2prom memory organi sation ..................................................................................73 6.2 product information field (rea d only).......................................................................................... ......74
philips semiconductors product s pecification rev. 3.0; may 2003 multiple protocol contactless reader ic cl rc632 3 confidential 6.3 register initialisati on files (rea d/write) ..................................................................................... ........75 6.3.1 start up register initialis ation file (r ead/write)............................................................................. ....75 6.3.2 shipment content of start up register initia lisation file ....................................................................76 6.3.3 register initialisati on file (rea d/write)...................................................................................... .........77 6.3.4 content of i code1 and iso15693 start up register values.........................................................78 6.4 crypto1 keys (write on ly)...................................................................................................... .............78 6.4.1 key fo rmat ..................................................................................................................... .....................79 6.4.2 storage of keys in the e2prom .................................................................................................. .......79 7 fifo buffer.................................................................................................................... .................80 7.1 overview....................................................................................................................... .......................80 7.2 accessing the fifo buffer ...................................................................................................... ............80 7.2.1 access rules................................................................................................................... ....................80 7.3 controlling the fifo-buffer .................................................................................................... .............81 7.4 status information abo ut the fifo -buffer ....................................................................................... ....81 7.5 register overview fifo buffer .................................................................................................. .........82 8 interrupt requ est system .....................................................................................................83 8.1 overview....................................................................................................................... .......................83 8.1.1 interrupt sour ces overview..................................................................................................... ............83 8.2 implementation of interr upt request handling................................................................................... .84 8.2.1 controlling interrupts and their status........................................................................................ .........84 8.2.2 accessing the inte rrupt registers .............................................................................................. .........84 8.3 configuration of pin irq ....................................................................................................... ..............84 8.4 register overview inte rrupt request system ..................................................................................... 85 9 timer unit ..................................................................................................................... ...................86 9.1 overview....................................................................................................................... .......................86 9.2 implementation of the time r unit ............................................................................................... .........87 9.2.1 block diagram .................................................................................................................. ...................87 9.2.2 controlling the timer unit..................................................................................................... ...............88 9.2.3 timer unit cl ock and period .................................................................................................... ...........88 9.2.4 status of t he timer unit....................................................................................................... ................89 9.2.5 timeslot period................................................................................................................. ...................89 9.3 usage of the timer unit ........................................................................................................ ..............90 9.3.1 time-out- and wa tch-dog-counter ................................................................................................ ....90 9.3.2 stop watch ..................................................................................................................... .....................91 9.3.3 programmable one- shot timer .................................................................................................... ......91 9.3.4 periodical trigger ............................................................................................................. ...................91 9.4 register overvi ew time r unit ................................................................................................... ..........92 10 power reduct ion modes .......................................................................................................... 93 10.1 hard powe r do wn ................................................................................................................ ...............93 10.2 soft powe r do wn................................................................................................................ .................93
philips semiconductors product s pecification rev. 3.0; may 2003 multiple protocol contactless reader ic cl rc632 4 confidential 10.3 stand by mode.................................................................................................................. ..................94 10.4 receiver po wer do wn............................................................................................................ .............94 11 start up phase ................................................................................................................. ............95 11.1 hard power do wn phase .......................................................................................................... ..........95 11.2 reset phase.................................................................................................................... ....................95 11.3 initialisi ng phase ............................................................................................................. ....................95 11.4 initialising the para llel interf ace-type ....................................................................................... ..........96 12 oscillator circuitry ........................................................................................................... .....97 13 transmitter pins tx1 and tx2 .................................................................................................98 13.1 configuration of tx1 and tx2................................................................................................... ..........98 13.2 operating distance versus power cons umption ................................................................................99 13.3 antenna driver output source re sistan ce ........................................................................................ .99 13.3.1 source resist ance t able ........................................................................................................ ..........100 13.3.2 formula for the s ource resistance.............................................................................................. .....101 13.3.3 calculating the effectiv e source resistance .................................................................................... 101 13.4 pulse wi dth .................................................................................................................... ...................102 14 receiver ci rcuitry ............................................................................................................. ......103 14.1 general........................................................................................................................ ......................103 14.2 block diagram .................................................................................................................. .................103 14.3 putting the receiver into operation ............................................................................................ ......104 14.3.1 automatic clock- q calibration .................................................................................................. ........104 14.3.2 amplifier...................................................................................................................... .......................105 14.3.3 correlation circuitry.......................................................................................................... .................106 14.3.4 evaluation and digi tizer circuitry ............................................................................................. .........106 15 serial signal switch ........................................................................................................... ....107 15.1 general........................................................................................................................ ......................107 15.2 block diagram .................................................................................................................. .................107 15.3 registers relevant for t he serial si gnal sw itch................................................................................ 108 15.3.1 active ant enna conc ept......................................................................................................... ...........109 15.3.2 driving two rf-parts ........................................................................................................... .............109 16 mifare ? higher b audrates ....................................................................................................110 17 iso14443 b..................................................................................................................... ..................111 18 cl rc632 co mmand set ........................................................................................................... ..112 18.1 general de scription............................................................................................................ ...............112 18.2 general be haviour .............................................................................................................. ..............112 18.3 cl rc632 comma nds over view ..................................................................................................... .112 18.3.1 basic states ................................................................................................................... ...................114 18.3.2 startup command 3f hex ....................................................................................................................114
philips semiconductors product s pecification rev. 3.0; may 2003 multiple protocol contactless reader ic cl rc632 5 confidential 18.3.3 idle command 00 hex ..........................................................................................................................114 18.4 commands for iso14443 a card communi cation ...........................................................................115 18.4.1 transmit command 1a hex ..................................................................................................................115 18.4.2 receive command 16 hex ...................................................................................................................119 18.4.3 transceive command 1e hex ..............................................................................................................122 18.4.4 states of the ca rd communication ............................................................................................... ....122 18.4.5 state diagram for the card communi cation .....................................................................................12 3 18.5 commands for i ? code1 and iso15693 label communica tion ......................................................124 18.5.1 transmit command 1a hex ..................................................................................................................124 18.5.2 receive command 16 hex ...................................................................................................................126 18.5.3 transceive command 1e hex ..............................................................................................................128 18.5.4 states of the label communi cation .............................................................................................. ....128 18.5.5 state diagram for the label communi cation ....................................................................................12 8 18.6 commands to acce ss the e2prom.................................................................................................. 130 18.6.1 writee2 command 01 hex ...................................................................................................................130 18.6.2 reade2 command 03 hex ...................................................................................................................132 18.7 diverse commands............................................................................................................... ............132 18.7.1 loadconfig command 07 hex ..............................................................................................................132 18.7.2 calccrc command 12 hex .................................................................................................................133 18.8 error handling during command ex ecution......................................................................................13 4 18.9 mifare ? classic security commands .............................................................................................135 18.9.1 loadkeye2 command 0b hex .............................................................................................................135 18.9.2 loadkey command 19 hex ..................................................................................................................135 18.9.3 authent1 command 0c hex .................................................................................................................136 18.9.4 authent2 command 14 hex ..................................................................................................................136 19 mifare ? classic authentica tion and crypto1..............................................................137 19.1 general........................................................................................................................ ......................137 19.2 crypto1 key handling ........................................................................................................... ............137 19.3 performing mifare ? classic auth entication....................................................................................138 20 typical appl ication............................................................................................................ ......139 20.1 circuit diagram................................................................................................................ ..................139 20.2 circuit description ............................................................................................................ .................140 20.2.1 emc low pa ss filter............................................................................................................ .............140 20.2.2 antenna ma tching ............................................................................................................... ..............140 20.2.3 receiving circuit .............................................................................................................. .................141 20.2.4 antenna coil................................................................................................................... ...................141 21 test signals ................................................................................................................... .............142 21.1 general........................................................................................................................ ......................142 21.2 measurements using the se rial signal switch .................................................................................142 21.2.1 tx-con trol..................................................................................................................... .....................143 21.2.2 rx-control ..................................................................................................................... .....................144
philips semiconductors product s pecification rev. 3.0; may 2003 multiple protocol contactless reader ic cl rc632 6 confidential 21.3 analog test -signals ............................................................................................................ ..............145 21.4 digital test -signal s ........................................................................................................... ................146 21.5 examples of iso14443a analog - and digital test signals .............................................................147 21.6 examples of i ? code1 analog- and digi tal test signals ..................................................................148 22 electrical cha racteristics ................................................................................................149 22.1 absolute maxi mum rati ngs....................................................................................................... ........149 22.2 operating condi tion range...................................................................................................... .........149 22.3 current cons umption ............................................................................................................ ............149 22.4 pin characteristics ............................................................................................................ ................150 22.4.1 input pin char acterist ics ...................................................................................................... .............150 22.4.2 digital output pin characteristics ............................................................................................. ........151 22.4.3 antenna driver output pin characte ristics ...................................................................................... .151 22.5 ac electrical ch aracteristics .................................................................................................. ...........152 22.5.1 ac symbols..................................................................................................................... ..................152 22.5.2 ac operating s pecification ..................................................................................................... ..........153 22.5.3 clock frequency ................................................................................................................ ...............157 23 e2prom charac teristics ........................................................................................................1 58 24 esd specifi cation .............................................................................................................. ........159 25 package ou tlines ............................................................................................................... ......160 25.1 so32 ........................................................................................................................... ......................160 26 disclaimers.................................................................................................................... ..............161 26.1 life support applications...................................................................................................... ..............161 26.2 licence policy ................................................................................................................. ..................161 27 revision histor y ............................................................................................................... .........162 27.1 update from revision 2.0 to revi sion 3.0....................................................................................... ..162 27.2 versions up to revision 3.0 .................................................................................................... ..........162 contact info rmation............................................................................................................ ..........................163
philips semiconductors product s pecification rev. 3.0; may 2003 multiple protocol contactless reader ic cl rc632 7 confidential 1 general information 1.1 scope this document describes the functionality of the cl rc632. it includes the functional and electrical specifications and gives details on how to design-in this device from system and hardware viewpoint. 1.2 general description the cl rc632 is member of a new family of highly integrated reader ics for contactless communication at 13.56 mhz. this reader ic family utilises an outstanding modulation and demodulation concept completely integrated for all kinds of passive contactless commu nication methods and protocols at 13.56 mhz. the cl rc632 is pin- compatible to the mf rc500, the mf rc530, the mf rc531 and the sl rc 400. the cl rc632 supports all layers of the iso14443 including the type a and type b communication scheme. the cl rc632 supports contactless communication using mifare ? higher baudrates. the receiver part provides a robust and efficient implementation of a demodulation and decoding circuitry for signals from iso14443 compatible transponders. the digital part handles the complete iso14443 framing and error detection (parity & crc). additionally it supports the fast mifare ? classic security algorithm to authenticate mifare ? classic (e.g. mifare ? standard, mifare ? light) products. the cl rc632 supports all layers of i ? code1 and iso 15693. the receiver part provides a robust and efficient implementation of a demodulation and decoding circuitry for signals from i ? code1 and iso 15693 compatible transponders. the digital part handles i ? code1 and iso 15693 framing and error detection (crc). the internal transmitter part is able to drive an anten na designed for proximity operating distance (up to 100 mm) directly without additional active circuitry. a comfortable parallel interface, which can be direct ly connected to any 8-bit -processor gives high flexibility for the reader/terminal design. additionally a spi compatible interface is supported.
philips semiconductors product s pecification rev. 3.0; may 2003 multiple protocol contactless reader ic cl rc632 8 confidential 1.3 features ? highly integrated analog circuitry to demodulate and decode card/label response ? buffered output drivers to connect an antenna wi th minimum number of external components ? proximity operating distance (up to 100 mm) ? supports iso 14443 a&b ? supports mifare ? dual interface card ics and supports mifare ? classic protocol ? supports contactless communication with mifare ? higher baudrates up to 424 kbaud ? supports i ? code1 and iso 15693 ? crypto1 and secure non-volatile internal key memory ? pin-compatible to the mf rc500, mf rc530, mf rc531 and the sl rc400 ? parallel -processor interface with internal address latch and irq line ? spi compatible interface ? flexible interrupt handling ? automatic detection of parallel -processor interface type ? comfortable 64 byte send and receive fifo-buffer ? hard reset with low power function ? power down mode per software ? programmable timer ? unique serial number ? user programmable start-up configuration ? bit- and byte-oriented framing ? independent power supply pins for digital, analog and transmitter part ? internal oscillator buffer to connect 13.56 mhz quartz, optimised for low phase jitter ? clock frequency filtering ? 3.3 v to 5 v operation for transmitter (antenna dr iver) in short range and proximity applications ? 3.3 v or 5v operation for the digital part 1.4 ordering information package type number name description cl rc632 01t/0fe so32 small outline package; 32 leads table 1-1: cl rc632 ordering information
philips semiconductors product s pecification rev. 3.0; may 2003 multiple protocol contactless reader ic cl rc632 9 confidential 2 block diagram parallel interface control (incl. automatic interface detection & synchronisation) control register bank 64 byte fifo serial data switch parallel/seriell converter programable timer d0 to d7 a0, a1, a2 ale n_wr, n_rd, n_cs 32 x 16 byte eeprom eeprom access control master key buffer cyrpto1 unit bit counter parity generation & check frame generation & check 32 bit pseudo random generator crc16/crc8 generation & check power down control command register state machine reset control dvdd dvss rstpd bit decoding bit coding mfin mfout transmitter control tx1 tx2 tvss tvdd fifo control q-clock generation power on detect avdd oscillator oscin oscout q-channel amplifier q-channel demodulator i-channel demodulator correlation and bit decoding amplitude rating i-channel amplifier reference voltage vmid rx analog test mux aux level shifters interrupt control voltage monitor & power on detect avss irq clock generation, filtering and distribution v + gnd v + gnd fi g ure 1-1: cl rc632 block dia g ram
philips semiconductors product s pecification rev. 3.0; may 2003 multiple protocol contactless reader ic cl rc632 10 confidential 3 pinning information 3.1 pin configuration pins denoted by bold letters are supplied by avdd a nd avss. pins drawn with bold lines are supplied by tvss and tvdd. all other pins are supplied by dvdd and dvss. 1 3 11 12 25 5 6 4 7 8 9 10 32 30 29 31 28 26 2 27 20 19 18 17 15 14 13 16 22 23 24 21 cl rc632 so32 oscin irq mfin mfout tx1 tvdd tx2 tvss ncs nwr nrd dvss d0 d1 d2 d3 oscout rstpd vmid rx avss aux avdd dvdd a2 a1 a0 ale d7 d6 d5 d4 figure 3-1: cl rc632 pin configuration for so32 package
philips semiconductors product s pecification rev. 3.0; may 2003 multiple protocol contactless reader ic cl rc632 11 confidential 3.2 pin description pin types: i...input; o ...output; pwr...power pin symbol type description 1 oscin i crystal oscillator input : input to the inverting am plifier of the oscillator. this pin is also the input for an externally generated clock (f osc = 13.56 mhz). 2 irq o interrupt request : output to signal an interrupt event 3 mfin i mifare ? interface input : accepts a digital, serial data stream according to iso14443a (mifare ? ) 4 2 mfout o mifare ? interface output : delivers a serial data stream according to iso14443a (mifare ? ) i ? code interface output : delivers a serial data stream according to i ? code1 and iso 15693 5 tx1 o transmitter 1 : delivers the modulated 13.56 mhz energy carrier 6 tvdd pwr transmitter power supply : supplies the output stage of tx1 and tx2 7 tx2 o transmitter 2 : delivers the modulated 13.56 mhz energy carrier 8 tvss pwr transmitter ground : supplies the output stage of tx1 and tx2 9 ncs i not chip select : selects and activates the -processor interface of the cl rc632 nwr i not write : strobe to write data (applied on d0 to d7) into the cl rc632 register r/nw i read not write : selects if a read or write cycle shall be performed. 10 1 nwrite i not write : selects if a read or write cycle shall be performed nrd i not read : strobe to read data from the cl rc6 32 register (applied on d0 to d7) nds i not data strobe : strobe for the read and the write cycle 11 1 ndstrb i not data strobe : strobe for the read and the write cycle 12 dvss pwr digital ground 13 d0 o master in slave out (miso), spi interface, d0 to d7 i/o 8 bit bi-directional data bus 13 ? 20 1 ad0 to ad7 i/o 8 bit bi-directional address and data bus ale i address latch enable : signal to latch ad0 to ad5 in to the internal address latch when high. as i address strobe : strobe signal to latch ad0 to ad 5 into the internal address latch when high. nastrb i not address strobe : strobe signal to latch ad0 to ad5 into the internal address latch when low. 21 1 nss i not slave select: strobe for the spi communication a0 i address line 0 : bit 0 of register address nwait o not wait: signals with low that an access-cycle ma y started and with high that it may be finished. 22 1 mosi i master out slave in, spi interface pin description (continued) 1 these pins offer different functionality according to the selected -processor in terface type. for detailed information, refer to chapter 4. 2 the sl rc400 uses the name sigout for the mfout pin. the clrc 632 functionality incl udes the test possibilities for the sl rc 400 using the pin mfout .
philips semiconductors product s pecification rev. 3.0; may 2003 multiple protocol contactless reader ic cl rc632 12 confidential pin symbol type description 23 a1 i address line 1 : bit 1 of register address a2 i address line 2 : bit 2 of register address 24 1 sck i serial clock : clock for the spi interface 25 dvdd piwr digital power supply 26 avdd pwr analog power supply 27 aux o auxiliary output : this pin delivers analog test signals. the signal delivered on this output may be selected by means of the testanaoutsel register . 28 avss pwr analog ground 29 rx i receiver input : input pin for the cards response, which is the load modulated 13.56 mhz energy carrier, that is coupled out from the antenna circuit. 30 vmid pwr internal reference voltage : this pin delivers the internal reference voltage. note : it has to be supported by means of a 100 nf block capacitor. 31 rstpd i reset and power down : when high, internal current sinks are switched off, the oscillator is inhibited, an d the input pads are disconnec ted from the outside world. with a negative edge on this pin the internal reset phase starts. 32 oscout o crystal oscillator output : output of the inverting am plifier of the oscillator. table 3-1: cl rc632 pin description
philips semiconductors product s pecification rev. 3.0; may 2003 multiple protocol contactless reader ic cl rc632 13 confidential 4 digital interface 4.1 overview of supported -processor interfaces the cl rc632 supports direct interfacing of various -processors. alternatively the enhanced parallel port (epp) of personal computers can be connected directly. the following t able shows the parallel interface signals supported by the cl rc632: bus control signals bus separated address and data bus multiplexed address and data bus control nrd, nwr, ncs nrd, nwr, ncs, ale address a0, a1, a2 ad0, ad1, ad2, ad3, ad4, ad5 separated read and write strobes data d0 ? d7 ad0 ? ad7 control r/nw, nds, ncs r/nw, nds, ncs, as address a0, a1, a2 ad0, ad1, ad2, ad3, ad4, ad5 common read and write strobe data d0 ? d7 ad0 ? ad7 control nwrite, ndstrb, nastrb, nwait address ad0, ad1, ad2, ad3, ad4, ad5 common read and write strobe with handshake (epp) data - ad0 ? ad7 table 4-1: supported -processor interface signals 4.2 automatic -processor interface type detection after every power-on or hard reset, the cl rc632 al so resets its parallel -processor interface mode and checks the current -processor interface type. the cl rc632 identifies the -processor interface by mean s of the logic levels on the control pins after the reset phase. this is done by a combination of fixed pin connections (see below) and a dedicated initialisation routine (see 11.4).
philips semiconductors product s pecification rev. 3.0; may 2003 multiple protocol contactless reader ic cl rc632 14 confidential 4.3 connection to different -processor types the connection to different -processor types is shown in the following table: parallel interface type separated read/write strobe common read/write strobe cl rc632 dedicated address bus multiplexed address bus dedicated address bus multiplexed address bus multiplexed address bus with handshake ale high ale high as nastrb a2 a2 low a2 low high a1 a1 high a1 high high a0 a0 high a0 low nwait nrd nrd nrd nds nds ndstrb nwr nwr nwr r/nw r/nw nwrite ncs ncs ncs ncs ncs low d7 ... d0 d7 ... d0 ad7 ... ad0 d7 ... d0 ad7 ... ad0 ad7 ... ad0 table 4-2: connection scheme for detecting the parallel interface type 4.3.1 separated read/write strobe for timing specification re fer to chapter 22.5.2.1. cl rc632 ncs a2 a1 a0 d0...d7 ale nrd nwr address decoder non multiplexed address multiplexed address/data (ad0...ad7) address latch enable (ale) low high high cl rc632 ncs d0...d7 ale nrd nwr address decoder address bus (a3...an) data bus (d0...d7) high read strobe (nrd) write strobe (nwr) read strobe (nrd) write strobe (nwr) a0...a2 address bus (a0...a2) fi g ure 4-1: connection to -processors with se p arated read/write strobes
philips semiconductors product s pecification rev. 3.0; may 2003 multiple protocol contactless reader ic cl rc632 15 confidential 4.3.2 common read/write strobe for timing specification re fer to chapter 22.5.2.2. cl rc632 ncs a0...a2 d0...d7 ale nrd nwr address decoder address bus (a3...an) data bus (d0...d7) high cl rc632 ncs a2 a1 a0 d0...d7 ale nrd nwr address decoder non multiplexed address multiplexed address/data (ad0...ad7) address strobe (as) low high low read/write (r/nw) data strobe (nds) data strobe (nds) read/write (r/nw) address bus (a0...a2) figure 4-2: connection to -processo rs with common read/write strobes
philips semiconductors product s pecification rev. 3.0; may 2003 multiple protocol contactless reader ic cl rc632 16 confidential 4.3.3 common read/write st robe and hand-shake mechanism: epp for timing specification re fer to chapter 22.5.2.3. remarks for epp: although in the standard for the epp no chip select signal is define d, the n_cs of the cl rc632 allows inhibiting the ndstrb signal. if not used, it shall be connected to dvss. after each power-on or hard reset the nwait signal ( delivered at pin a0) is high impedance. nwait will be defined at the first negative edge applied to nastrb after the reset phase. the cl rc632 does not support read address cycle. cl rc632 ncs a2 a1 a0 d0...d7 ale nrd nwr multiplexed address/data (ad1...ad8) address strobe (nastrb) high high nwait read/write (nwrite) data strobe (ndstrb) low figure 4-3: connection to -processors with common read/write strobes and hand-shake
philips semiconductors product s pecification rev. 3.0; may 2003 multiple protocol contactless reader ic cl rc632 17 confidential 4.4 spi compatible interface additionally the serial peripheral interface (spi) will be supported. the cl rc632 acts as a slave during the spi communication. the spi clock sck has to be g enerated by the master. data communication from the master to the slave uses the line mosi. line miso is used to send data back from the cl rc632 to the master. cl rc632 spi interface ale nss a2 sck a1 low a0 mosi nrd high nwr high ncs low d7 ... d1 do not connect d0 miso table 4-3: spi compatible interface the following table shows the -processor connect ion to the cl rc632 using the spi interface. cl rc632 ncs a2 a1 a0 d0 ale nss sck low mosi low miso figure 4-4: connection to -processors with spi
philips semiconductors product s pecification rev. 3.0; may 2003 multiple protocol contactless reader ic cl rc632 18 confidential remarks for spi: the implemented spi interface is according to a standard spi interface. the cl rc632 can only be addressed as a slave. read data: to read out data using the spi interface the following structure has to be used. it is possible to read out up to n-data bytes. the first sent byte defines both, the mode itself and the address. byte 0 byte 1 byte 2 ??.. byte n byte n+1 mosi adr 0 adr 1 adr. 2 ??. adr n 00 miso xx data 0 data 1 ?? data n-1 data n the address byte has to fulfil the following format. the m sb bit of the first byte sets the used mode. to read data from the cl rc632 the msb bit is set to 1. t he bits 6-1 define the address and the last bit should be set to 0. according to scheme above, the last sent byte has been set to 0. address (mosi) bit 7, msb bit 6 - bit 1 bit 0 byte 0 1 address rfu (0) byte 1 to byte n rfu (0) address rfu (0) byte n+1 0 0 0 write data: to write data to the cl rc632 using the spi interface the following structure has to be used. it is possible to write out up to n-data bytes. the first send byte defines both, the mode itself and the address. byte 0 byte 1 byte 2 ???. byte n byte n+1 mosi adr data 0 data 1 ???. data n-1 data n miso xx xx xx ???. xx xx the address byte has to fulfil the following format. the m sb bit of the first byte sets the used mode. to write data to the cl rc632 the msb bit is set to 0. the bits 6-1 define the address and the last bit should be set to 0.
philips semiconductors product s pecification rev. 3.0; may 2003 multiple protocol contactless reader ic cl rc632 19 confidential the spi write mode writes all data to the same address as defined in byte 0. this allows an effective data writ ing to the cl rc632?s fifo buffer. address line (mosi) msb bit 6 - bit 1 bit 0 byte 0 0 address rfu (0) byte 1 to byte n+1 data note: the data bus pins d7?d1 have to be disconnected. for timing specification re fer to chapter 22.5.2.4
philips semiconductors product s pecification rev. 3.0; may 2003 multiple protocol contactless reader ic cl rc632 20 confidential 5 cl rc632 register set 5.1 cl rc632 registers overview page address hex register name function 0 page selects the register page 1 command starts (and stops) the command execution 2 fifodata in- and output of 64 byte fifo buffer 3 primarystatus status flags of the receiver and transmitter and of the fifo buffer 4 fifolength number of bytes buffered in the fifo 5 secondarystatus diverse status flags 6 interrupten control bits to enable and disable passing of interrupt requests page 0: command and status 7 interruptrq interrupt request flags 8 page selects the register page 9 control diverse control flags e.g.: timer, power saving a errorflag error flags showing the error stat us of the last command executed b collpos bit position of the first bit colli sion detected on the rf-interface c timervalue actual value of the timer d crcresultlsb lsb of the crc-coprocessor register e crcresultmsb msb of the crc-coprocessor register page 1: control and status f bitframing adjustments for bit oriented frames 10 page selects the register page 11 txcontrol controls the logical behaviour of the antenna driver pins tx1 and tx2 12 cwconductance selects the conductance of the antenna driver pins tx1 and tx2 13 modconductance defines the driver output conductance 14 codercontrol sets the clock rate and the coding mode 15 modwidth selects the width of the modulation pulse 16 modwidthsof selects the width of the modulation pulse for sof (i ? code fast-mode) page 2: transmitter and coder control 17 typebframing defines the framing for iso14443-b communication 18 page selects the register page 19 rxcontrol1 controls receiver behaviour 1a decodercontrol controls decoder behaviour 1b bitphase selects the bit-phase between transmitter and receiver clock 1c rxthreshold selects thresholds for the bit decoder 1d bpskdemcontrol control bpsk receiver behaviour 1e rxcontrol2 controls decoder behaviour and defines the input source for the receiver page 3: receiver and decoder control 1f clockqcontrol controls clock generation for the 90 phase shifted q-channel clock cl rc632 register set (continued)
philips semiconductors product s pecification rev. 3.0; may 2003 multiple protocol contactless reader ic cl rc632 21 confidential page address hex register name function 20 page selects the register page 21 rxwait selects the time interval afte r transmission, before receiver starts 22 channelredundancy selects the kind and mode of checki ng the data integrity on the rf- channel 23 crcpresetlsb lsb of the pre-set value for the crc register 24 crcpresetmsb msb of the pre-set value for the crc register 25 timeslotperiod selects the time between automatically mitted frames 26 mfoutselect selects internal signal applied to pin mfout, includes the msb of value timeslotperiod see register 0x25 page 4: rf-timing and channel redundancy 27 preset27 these values shall not be changed 28 page selects the register page 29 fifolevel defines level for fifo over? and underflow warning 2a timerclock selects the divider for the timer clock 2b timercontrol selects start an d stop conditions for the timer 2c timerreload defines the pre-set value for the timer 2d irqpinconfig configures the output stage of pin irq 2e preset2e these values shall not be changed page 5: fifo, timer and irq-pin configuration 2f preset2f these values shall not be changed 30 page selects the register page 31 rfu reserved for future use 32 rfu reserved for future use 33 rfu reserved for future use 34 rfu reserved for future use 35 rfu reserved for future use 36 rfu reserved for future use page 6: rfu 37 rfu reserved for future use 38 page selects the register page 39 rfu reserved for future use 3a testanaselect selects analog test mode 3b rfu reserved for future use 3c rfu reserved for future use 3d testdigiselect selects digital test mode 3e rfu reserved for future use page 7: test control 3f rfu reserved for future use table 5-1: cl rc632 register overview
philips semiconductors product s pecification rev. 3.0; may 2003 multiple protocol contactless reader ic cl rc632 22 confidential 5.1.1 register bit behaviour bits and flags for different registers behave differently , depending on their functions. in principle bits with same behaviour are grouped in common registers. abbreviation behaviour description r/w read and write these bits can be written and read by the -processor. since they are used only for control means, ther e content is not influenced by internal state machines, e.g. the timerreload-register may be written and read by the - processor. it will also be read by internal state machines, but never changed by them. dy dynamic these bits can be written and read by t he -processor. nevertheless, they may also be written automatically by internal state machines, e.g. the command- register changes its value automatically a fter the execution of the actual command. r read only these registers hold flags, which value is determined by internal states only, e.g. the errorflag-register can not be written from external but shows internal states. w write only these registers are used for control means only. they may be written by the - processor but can not be read. reading these registers returns an undefined value, e.g. the testanaselect-register is used to determine the signal on pin aux, but it is not possible to read its content. table 5-2: behaviour of register bits and its designation
philips semiconductors product s pecification rev. 3.0; may 2003 multiple protocol contactless reader ic cl rc632 23 confidential 5.2 register description 5.2.1 page 0: command and status 5.2.1.1 page register selects the register page. name: page address: 0x 00, 0x08, 0x10, 0x18, 0x20, 0x28, 0x30, 0x38 reset value: 10000000, 0x80 7 6 5 4 3 2 1 0 usepage select 0 0 0 0 pageselect access rights r/w r/w r/w r/w r/w r/w r/w r/w description of the bits bit symbol function 7 usepageselect if set to 1, the value of pageselect is used as register address a5, a4, and a3. the lsbbits of the register address are def ined by the address pins or the internal address latch, respectively. if set to 0, the whole content of the internal address latch defines the register address. the address pins are used as described in table 4-2. 6-3 0000 reserved for future use. 2-0 pageselect the value of pageselect is used only if usepageselect is set to 1. in this case, it specifies the register page (which is a5, a4, and a3 of the register address).
philips semiconductors product s pecification rev. 3.0; may 2003 multiple protocol contactless reader ic cl rc632 24 confidential 5.2.1.2 command register starts and stops the command execution. name: command address: 0x01 reset value:x0000000, 0xx0 7 6 5 4 3 2 1 0 ifdetect busy 0 command access rights r r dy dy dy dy dy dy description of the bits bit symbol function 7 ifdetectbusy shows the status of interface detection logic: set to 0 means ?interface detection finished successfully?, set to 1 signs ?interface detection ongoing?. 6 0 reserved for future use. 5-0 command activates a command according the command code. reading this register shows, which command is actually executed.
philips semiconductors product s pecification rev. 3.0; may 2003 multiple protocol contactless reader ic cl rc632 25 confidential 5.2.1.3 fifodata register in- and output of the 64 byte fifo buffer. name: fifodata address: 0x02 reset value: xxxxxxxx, 0xxx 7 6 5 4 3 2 1 0 fifodata access rights dy dy dy dy dy dy dy dy description of the bits bit symbol function 7-0 fifodata data input and output port for the internal 64 byte fifo buffer. the fifo buffer acts as parallel in/parallel out conver ter for all data stream in- and outputs.
philips semiconductors product s pecification rev. 3.0; may 2003 multiple protocol contactless reader ic cl rc632 26 confidential 5.2.1.4 primarystatus register status flags of the receiver, transmitter and the fifo buffer. name: primarystatus address: 0x03 reset value: 00000101, 0x05 7 6 5 4 3 2 1 0 0 modemstate irq err hialert loalert access rights r r r r r r r r description of the bits bit symbol function 7 0 reserved for future use. modemstate shows the state of the tr ansmitter and receiver state machines. state name of state description 000 idle neither the transmitter nor the receiver is in operation, since none of them is started or since none of them has input data. 001 txsof transmitting the ?start of frame? pattern. 010 txdata transmitting data from the fifo buffer (or redundancy check bits). 011 txeof transmitting the ?end of frame? pattern. gotorx1 intermediate state, when receiver starts. 100 gotorx2 intermediate state, when receiver finishes. 101 preparerx waiting until the time period selected in the rxwait register is expired. 110 awaitingrx receiver activated; awaiting an input signal at pin rx. 6-4 modemstate 111 receiving receiving data. 3 irq this bit shows, if any interrupt sour ce requests attention (with respect to the setting of the interrupt enable flags in the interrupten register ). 2 err this bit is set to 1, if any error flag in the errorflag register is set. 1 hialert is set to 1, when the number of bytes stored in the fifo buffer fulfil the following equation: waterlevel fifolength hialert ? = ) 64 ( example: fifolength=60, waterlevel=4 ? hialert =1 fifolength=59, waterlevel=4 ? hialert =0 0 loalert is set to 1, when the number of byte s stored in the fifo buffer fulfil the following equation: waterlevel fifolength loalert = example: fifolength=4, waterlevel=4 ? loalert =1 fifolength=5, waterlevel=4 ? loalert =0
philips semiconductors product s pecification rev. 3.0; may 2003 multiple protocol contactless reader ic cl rc632 27 confidential 5.2.1.5 fifolength register number of bytes buffered in the fifo. name: fifolength address: 0x04 reset value: 00000000, 0x00 7 6 5 4 3 2 1 0 0 fifolength access rights r r r r r r r r description of the bits bit symbol function 7 0 reserved for future use. 6-0 fifolength indicates the number of bytes stored in the fifo buffer. writing to the fifodata register increments, reading decrements fifolength.
philips semiconductors product s pecification rev. 3.0; may 2003 multiple protocol contactless reader ic cl rc632 28 confidential 5.2.1.6 secondarystatus register diverse status flags. name: secondarystatus address: 0x05 reset value: 01100000, 0x60 7 6 5 4 3 2 1 0 trunning e2ready crcready 0 0 rxlastbits access rights r r r r r r r r description of the bits bit symbol function 7 trunning if set to 1, the cl rc632?s timer uni t is running, e.g. the counter will decrement the timer value register with the next timer clock. 6 e2ready if set to 1, the cl rc632 has finished programming the e2prom. 5 crcready if set to 1, the cl rc632 has finished calculating the crc. 4-3 00 reserved for future use. 2-0 rxlastbits show the number of valid bits in the last received byte. if zero, the whole byte is valid.
philips semiconductors product s pecification rev. 3.0; may 2003 multiple protocol contactless reader ic cl rc632 29 confidential 5.2.1.7 interrupten register control bits to enable and disable passing of interrupt requests. name: interrupten address: 0x06 reset value: 00000000, 0x00 7 6 5 4 3 2 1 0 setien 0 timerien txien rxien idleien hialertien loalertien access rights w r/w r/w r/w r/ w r/w r/w r/w description of the bits bit symbol function 7 setien set to 1 setien defines that the marked bits in the interrupten register are set, set to 0 clears the marked bits. 6 0 reserved for future use. 5 timerien allows the timer interrupt request (indicated by bit timerirq ) to be propagated to pin irq. this bit can not be set or cl eared directly but only by means of bit setien . 4 txien allows the transmitter in terrupt request (indicated by bit txirq ) to be propagated to pin irq. this bit can not be set or cleared directly but only by means of bit setien . 3 rxien allows the receiver inte rrupt request (indicated by bit rxirq ) to be propagated to pin irq. this bit can not be set or cl eared directly but only by means of bit setien . 2 idleien allows the idle interrupt request (indicated by bit idleirq ) to be propagated to pin irq. this bit can not be set or cleared directly but only by means of bit setien . 1 hialertien allows the high alert interrupt request (indicated by bit hialertirq ) to be propagated to pin irq. this bit can not be set or cleared directly but only by means of bit setien . 0 loalertien allows the low alert in terrupt request (indicated by bit loalertirq ) to be propagated to pin irq. this bit can not be set or cleared directly but only by means of bit setien .
philips semiconductors product s pecification rev. 3.0; may 2003 multiple protocol contactless reader ic cl rc632 30 confidential 5.2.1.8 interruptrq register interrupt request flags. name: interruptrq address: 0x07 reset value: 00000000, 0x00 7 6 5 4 3 2 1 0 setirq 0 timerirq txirq rxir q idleirq hialertirq loalertirq access rights w r/w dy dy dy dy dy dy description of the bits bit symbol function 7 setirq set to 1, setirq defines that the marked bits in the interruptrq register are set. set to 0 setirq defines, that the marked bits in the interruptrq register are cleared. 6 0 reserved for future use. 5 timerirq set to 1, when the timer decrements the timervalue register to zero. 4 txirq set to 1, when one of the following events occurs: transceive command : all data transmitted. auth1 and auth2 command : all data transmitted. writee2 command : all data is programmed. calccrc command : all data is processed. 3 rxirq this bit is set to 1, when the receiver terminates. 2 idleirq this bit is set to 1, when a co mmand terminates by itself e.g. when the command register changes its value from any command to the idle command . if an unknown command is started bit idleirq is set. starting the idle command by the -processor does not set bit idleirq . 1 hialertirq this bit is set to 1, when bit hialert is set. in opposite to hialert , hialertirq stores this event and can only be reset by means of bit setirq . 0 loalertirq this bit is set to 1, when bit loalert is set. in opposite to loalert , loalertirq stores this event and can only be reset by means of bit setirq .
philips semiconductors product s pecification rev. 3.0; may 2003 multiple protocol contactless reader ic cl rc632 31 confidential 5.2.2 page 1: control and status 5.2.2.1 page register selects the register page. see 5.2.1.1 page register . 5.2.2.2 control register diverse control flags, e.g.: timer, power saving. name: control address: 0x09 reset value: 00000000, 0x00 7 6 5 4 3 2 1 0 0 0 standby powerdown crypto1on tstopnow tstartnow flushfifo access rights r/w r/w dy dy dy w w w description of the bits bit symbol function 7-6 00 reserved for future use 5 standby setting this bit to 1 enters the so ft powerdown mode. this means, internal current consuming blocks are switched off, the oscillator keeps running. 4 powerdown setting this bit to 1 enters the soft powerdown mode. this means, internal current consuming bloc ks are switched off in cluding the oscillator. 3 crypto1on this bit indicates that the crypto1 unit is switched on and therefore all data communication with the card is encrypted. this bit can only be set to 1 by a successful execution of the authent2 command. 2 tstopnow setting this bit to 1 stops the timer immediately. reading this bit will always return 0. 1 tstartnow setting this bit to 1 starts the timer immediately. reading this bit will always return 0. 0 flushfifo setting this bit to 1clears the in ternal fifo-buffer?s read- and write-pointer ( fifolength becomes 0) and the flag fifoovfl immediately. reading this bit will always return 0.
philips semiconductors product s pecification rev. 3.0; may 2003 multiple protocol contactless reader ic cl rc632 32 confidential 5.2.2.3 errorflag register error flags showing the error stat us of the last executed command. name: errorflag address: 0x0a reset value: 01000000, 0x40 7 6 5 4 3 2 1 0 0 keyerr accesserr fifoovfl crcerr framingerr parityerr collerr access rights r r r r r r r r description of the bits bit symbol function 7 0 reserved for future use. 6 keyerr this bit is set to 1, if the loadkey e2 or the loadkey command recognises, that the input data is not coded according to the key format definition. this bit is set to 0 starting the loadkeye2 or the loadkey command. 5 accesserr this bit is set to 1, if t he access rights to the e2prom are violated. this bit is set to 0 starting an e2prom related command. 4 fifoovfl this bit is set to 1, if the -proces sor or a cl rc632?s internal state machine (e.g. receiver) tries to write data into the fi fo buffer although the fifo buffer is already full. 3 crcerr this bit is set to 1, if rxcrcen is set and the crc fails. it is cleared to 0 automatically at receiver start phase during the state preparerx. 2 framingerr this bit is set to 1, if the sof is incorrect. it is cleared automatically at receiver start (that is during the state preparerx). 1 parityerr this bit is set to 1, if the parit y check has failed. it is cleared automatically at receiver start (that is during the state preparerx). 0 collerr this bit is set to 1, if a bit-collis ion is detected. it is cleared automatically at receiver start (that is during the state preparerx). note: only valid for communication according to iso14443 a.
philips semiconductors product s pecification rev. 3.0; may 2003 multiple protocol contactless reader ic cl rc632 33 confidential 5.2.2.4 collpos register bit position of the first bit collision detected on the rf- interface. name: collpos address: 0x0b reset value: 00000000, 0x00 7 6 5 4 3 2 1 0 collpos access rights r r r r r r r r description of the bits bit symbol function 7-0 collpos this register shows the bit positio n of the first detected collision in a received frame. example: 0x00 indicates a bit collision in the start bit 0x01 indicates a bit collision in the 1 st bit 0x08 indicates a bit collision in the 8 th bit note: for iso14443b a bit collision is no t indicated in the collpos register.
philips semiconductors product s pecification rev. 3.0; may 2003 multiple protocol contactless reader ic cl rc632 34 confidential 5.2.2.5 timervalue register actual value of the timer. name: timervalue address:0x0c reset value: xxxxxxxx, 0xxx 7 6 5 4 3 2 1 0 timervalue access rights r r r r r r r r description of the bits bit symbol function 7-0 timervalue this register shows the actual value of the timer counter.
philips semiconductors product s pecification rev. 3.0; may 2003 multiple protocol contactless reader ic cl rc632 35 confidential 5.2.2.6 crcresultlsb register lsb of the crc-coprocessor register. name: crcresultlsb address: 0x0d reset value: xxxxxxxx, 0xxx 7 6 5 4 3 2 1 0 crcresultlsb access rights r r r r r r r r description of the bits bit symbol function 7-0 crcresultlsb this register shows the actual value of the least significant byte of the crc register. it is valid only if bit crcready is set to 1.
philips semiconductors product s pecification rev. 3.0; may 2003 multiple protocol contactless reader ic cl rc632 36 confidential 5.2.2.7 crcresultmsb register msb of the crc-coprocessor register. name: crcresultmsb address: 0x0e reset value: xxxxxxxx, 0xxx 7 6 5 4 3 2 1 0 crcresultmsb access rights r r r r r r r r description of the bits bit symbol function 7-0 crcresultmsb this register shows the actual value of the most signifi cant byte of the crc register. it is valid only if bit crcready is set to 1. for 8-bit crc calculation the registers value is undefined.
philips semiconductors product s pecification rev. 3.0; may 2003 multiple protocol contactless reader ic cl rc632 37 confidential 5.2.2.8 bitframing register adjustments for bit oriented frames. name: bitframing address: 0x0f reset value: 00000000, 0x00 7 6 5 4 3 2 1 0 0 rxalign 0 txlastbits access rights r/w dy dy dy r/w dy dy dy description of the bits bit symbol function 7 0 reserved for future use 6-4 rxalign used for reception of bit oriented frames: rxalign defines the bit position for the first bit received to be stored in the fifo. further received bits are stored in the following bit positions. after reception, rxalign is cleared automatically. example: rxalign = 0: the lsb of th e received bit is stored at bit 0, second received bit is stored at bit position 1 rxalign = 1: the lsb of the received bit is stored at bit 1, second received bit is stored at bit position 2 rxalign = 7: the lsb of the received bit is stored at bit 7, second received bit is stored in the following byte at bit position 0 3 0 reserved for future use 2-0 txlastbits used for transmission of bit oriented frames: txlastbits defines the number of bits of the last byte that shall be transmitt ed. a 000 indicates that all bits of the last byte shall be transmitted. after transmission, txlastbits is cleared automatically.
philips semiconductors product s pecification rev. 3.0; may 2003 multiple protocol contactless reader ic cl rc632 38 confidential 5.2.3 page 2: transmitter and control 5.2.3.1 page register selects the register page. see 5.2.1.1 page register . 5.2.3.2 txcontrol register controls the logical behaviour of the antenna pin tx1 and tx2. name: txcontrol address: 0x11 reset value: 01011000, 0x58 7 6 5 4 3 2 1 0 0 modulatorsource force 100ask tx2inv tx2cw tx2rfen tx1rfen access rights r/w r/w r/w r/w r/w r/w r/w r/w description of the bits bit symbol function 7 0 this value shall not be changed 6-5 modulator source selects the source for the modulator input: 00: low 01: high 10: internal coder 11: pin mfin 4 force100ask set to 1, force100ask forces a 100% ask modulation independent of the setting in the modconductance register. 3 tx2inv set to 1, the output signal on pi n tx2 will deliver an inverted 13.56 mhz energy carrier. 2 tx2cw set to 1, the output signal on pin tx 2 will deliver continuously the un-modulated 13.56 mhz energy carrier. setting tx2cw to 0 enables modulation of the 13.56 mhz energy carrier. 1 tx2rfen set to 1, the output signal on pin tx2 will deliver the 13.56 mhz energy carrier modulated by the transmission data. if tx2rfen is 0, tx2 drives a constant output level. 0 tx1rfen set to 1, the output signal on pin tx1 will deliver the 13.56 mhz energy carrier modulated by the transmission data. if tx1rfen is 0, tx1 drives a constant output level.
philips semiconductors product s pecification rev. 3.0; may 2003 multiple protocol contactless reader ic cl rc632 39 confidential 5.2.3.3 cwconduct ance register selects the conductance of the antenna driver pins tx1 and tx2. name: cwconductance address: 0x12 reset value: 00111111, 0x3f 7 6 5 4 3 2 1 0 0 0 gscfgcw access rights r/w r/w r/w r/w r/w r/w r/w r/w description of the bits bit symbol function 7-6 00 these values shall not be changed 5-0 gscfgcw the value of this register defines the conductance of the output driver. this may be used to regulate the output power and subsequently current consumption and operating distance. note: for detailed information about gscfgcw see 13.3
philips semiconductors product s pecification rev. 3.0; may 2003 multiple protocol contactless reader ic cl rc632 40 confidential 5.2.3.4 modconductance register defines the driver output conductance. name: modconductance address: 0x13 reset value: 00111111, 0x03f 7 6 5 4 3 2 1 0 0 0 gscfgmod access rights r/w r/w r/w r/w r/w r/w r/w r/w description of the bits bit symbol function 7-6 00 these values shall not be changed 5-0 gscfgmod the value of this register defines t he conductance of the output driver for the time of modulation. this may be used to regulate the modulation index. note: if force100ask is set to one, t he value of gscfgmod has no effect. for detailed information about gscfgmod see 13.3
philips semiconductors product s pecification rev. 3.0; may 2003 multiple protocol contactless reader ic cl rc632 41 confidential 5.2.3.5 codercontrol register sets the clock rate and the coding mode name: codercontrol address:0x14 reset value: 00011001, 0x19 7 6 5 4 3 2 1 0 sendone pulse 0 coderrate txcoding access rights r/w r/w r/w r/w r/w r/w r/w r/w description of the bits bit symbol function 7 sendonepulse set to 1, forces to generate only one mudulation (for iso 15693 only). this is used to switch to the next timeslot if the inventory command is used. this bit is not cleared automatically, it has to be re-set to 0 by the user. 6 0 these values shall not be changed 5-3 coderrate this register defines the clock rate for coder circuit 000: mifare ? 848 kbaud 001: mifare ? 424 kbaud 010: mifare ? 212 kbaud 011: mifare ? 106 kbaud; iso14443 a 100: iso 14443-b 101: for i code1 standard mode and iso 15693 (~52.97khz) 110: for i code1 fast mode (~26.48khz) 111: rfu 2-0 txcoding this register defines the bi t coding mode and framing during transmission 000: nrz according iso14443-b 001: mifare ? , iso14443-a, (miller coded) 010: rfu 011: rfu 100: for i code1 standard mode (1 out of 256 coding) 101: for i code1 fast mode (rz coding) 110: for iso 15693 standard mode (1 out of 256 coding) 111: for iso 15693 fast mode (1 out of 4 coding)
philips semiconductors product s pecification rev. 3.0; may 2003 multiple protocol contactless reader ic cl rc632 42 confidential 5.2.3.6 modwidth register selects the width of the modulation pulse. name: modwidth address: 0x15 reset value: 00010011, 0x13 7 6 5 4 3 2 1 0 modwidth access rights r/w r/w r/w r/w r/w r/w r/w r/w description of the bits bit symbol function 7-0 modwidth this register defines the wi dth of the modulation pulse according to t mod = 2 ? (modwidth +1) / fc. 5.2.3.7 modwidthsof register name: modwidthsof address: 0x16 reset value: 00111111, 0x3f 7 6 5 4 3 2 1 0 modwidthsof access rights r/w r/w r/w r/w r/w r/w r/w r/w description of the bits bit symbol function 7-0 modwidthsof this register defines t he width of the modulation pulse for sof t mod = 2 ? (modwidth +1) / fc . register setting: mifare? & iso14443: 0x3f(modulation width sof: 9.44 s). i ? code 1 standard mode: 0x3f (modulation width sof: 9.44 s). i ? code 1 fast mode: 0x73 (modulation width sof: 18.88 s). iso 15693: 0x3f (modulation width sof: 9.44 s).
philips semiconductors product s pecification rev. 3.0; may 2003 multiple protocol contactless reader ic cl rc632 43 confidential 5.2.3.8 typebframing defines the framing for iso 14443 b communication name: typebframing address: 0x17 reset value: 00111011, 0x3b 7 6 5 4 3 2 1 0 notx sof notx eof eof width charspacing sofwidth access rights r/w r/w r/w r/w r/w r/w r/w r/w description of the bits bit symbol function 7 notxsof set to 1 txcoder suppresses the sof 6 notxeof set to 1 txcoder suppresses the eof 5 eofwidth 0: set the eof to a length of 10 etu 1: set the eof to a length of 11 etu 4-2 charspacing set the length of the egt length between 0 and 7 etu. 1-0 sofwidth 00: set the sof to a length of 10 etu low and 2 etu high 01: set the sof to a length of 10 etu low and 3 etu high 10: set the sof to a length of 11 etu low and 2 etu high 11: set the sof to a length of 11 etu low and 3 etu high
philips semiconductors product s pecification rev. 3.0; may 2003 multiple protocol contactless reader ic cl rc632 44 confidential 5.2.4 page 3: receiver and decoder control 5.2.4.1 page register selects the register page. see 5.2.1.1 page register . 5.2.4.2 rxcontrol1 register controls receiver behaviour. name: rxcontrol1 address: 0x19 reset value: 01110011, 0x73 7 6 5 4 3 2 1 0 subcpulses iso selection lpoff gain access rights r/w r/w r/w r/w r/w r/w r/w r/w description of the bits bit symbol function 7-5 subcpulses defines the number of subcarrier pulses per bit 000: 1 pulse 001: 2 pulses 010: 4 pulses 011: 8 pulses iso14443a&b 100: 16 pulses i ? code 1 , iso15693 101: rfu 110: rfu 111: rfu 4-3 iso selection 00: rfu 10: iso 14443 a&b 01: i ? code 1 , iso15693 11: rfu 2 lpoff switches off a lowpassfilt er at the internal amplifier. 1-0 gain this register defines t he receivers signal voltage gain factor: 00: 20 db 01: 24 db 10: 31 db 11: 35 db
philips semiconductors product s pecification rev. 3.0; may 2003 multiple protocol contactless reader ic cl rc632 45 confidential 5.2.4.3 decodercontrol register controls decoder behaviour. name: decodercontrol address: 0x1a reset value: 00001000, 0x08 7 6 5 4 3 2 1 0 0 rxmultiple zeroafter coll rxframing rxinvert 0 rxcoding access rights r/w r/w r/w r/w r/w r/w r/w r/w description of the bits bit symbol function 7 0 these values shall not be changed 6 rxmultiple if set to 0, after receiving of the frame the receiver is deactivated if set to 1, it is possible to receive more than one frame 5 zeroafter coll if set to 1, any bits received after a bi t-collision are masked to zero. this eases resolving the anti-collision procedure defined in iso14443-a. 4-3 rxframing 00: for i ? code 1 01: mifare ? , iso14443a 10: iso 15693 11: iso14443b 2 rxinvert if set to 0, a modulation at the first half bit results a logic 1 (according i ? code1) if set to 1, a modulation at the first half bit results a logic 0 (according iso15693) 1 0 these values shall not be changed 0 rxcoding 0: manchester coding 1: bpsk coding
philips semiconductors product s pecification rev. 3.0; may 2003 multiple protocol contactless reader ic cl rc632 46 confidential 5.2.4.4 bitphase register selects the bit-phase between transmitter and receiver clock. name: bitphase address: 0x1b reset value: 10101101, 0xad 7 6 5 4 3 2 1 0 bitphase access rights r/w r/w r/w r/w r/w r/w r/w r/w description of the bits bit symbol function 7-0 bitphase defines the phase relation between transmitter and receiver clock. note : the correct value of this register is essential for proper operation.
philips semiconductors product s pecification rev. 3.0; may 2003 multiple protocol contactless reader ic cl rc632 47 confidential 5.2.4.5 rxthreshold register selects thresholds for the bit decoder. name: rxthreshold address: 0x1c reset value: 11111111, 0xff 7 6 5 4 3 2 1 0 minlevel colllevel access rights r/w r/w r/w r/w r/w r/w r/w r/w description of the bits bit symbol function 7-4 minlevel defines the minimum signal strength at the decoder input that shall be accepted. if the signal strength is below this level, it is not evaluated. 3-0 colllevel defines the minimum signal strengt h at the decoder input that has to be reached by the weaker half-bit of the manchester -coded signal to generate a bit-collision relatively to the amplitude of the stronger half-bit.
philips semiconductors product s pecification rev. 3.0; may 2003 multiple protocol contactless reader ic cl rc632 48 confidential 5.2.4.6 bpskdemcontrol controls bpsk demodulation name: bpskdemcontrol address: 0x 1d reset value: 00011110, 0x1e 7 6 5 4 3 2 1 0 norx sof norx egt norx eof filter ampdet taud taub access rights r/w r/w r/w r/w r/w r/w r/w r/w description of the bits bit symbol function 7 norxsof if set to 1 a missing sof in the receiving data stream will be ignored and no framing error indicated 6 norxegt if set to 1 a too short or too long egt in the receiving data stream will be ignored and no framing error indicated 5 norxeof if set to 1 a missing eof in the re ceiving data stream pr oduces will be ignored and no framing error indicated 4 filterampdet switches on a highpassfilter for amplitude detection 3-2 taud change time-constant of internal pll during data receiving 1-0 taub change time-constant of internal pll during burst
philips semiconductors product s pecification rev. 3.0; may 2003 multiple protocol contactless reader ic cl rc632 49 confidential 5.2.4.7 rxcontrol2 register controls decoder behaviour and defines the input source for the receiver. name:rxcontrol2 address: 0x1e reset value: 01000001, 0x41 7 6 5 4 3 2 1 0 rcvclkseli rxautopd 0 0 0 0 decodersource access rights r/w r/w r/w r/w r/w r/w r/w r/w description of the bits bit symbol function 7 rcvclkseli if set to 1, the i-clock is used for the receiver clock. set to 0 indicates, that the q-clock is used. i-clock and q-clock are 90 phase shifted to each other 6 rxautopd if set to 1, the receiver circuit is automatically switched on before receiving and switched off afterwards. this may be used to reduce current consumption. if set to 0, the receiver is always activated. 5-2 0000 these values shall not be changed 1-0 decodersource selects the source for the decoder input: 00: low 01: internal demodulator 10: a subcarrier modulated manchester coded signal at pin mfin 11: a baseband manchester coded signal at pin mfin
philips semiconductors product s pecification rev. 3.0; may 2003 multiple protocol contactless reader ic cl rc632 50 confidential 5.2.4.8 clockqcontrol register controls clock generation for the 90 phase shifted q-channel clock. name: clockqcontrol address: 0x1f reset value: 000xxxxx, 0xxx 7 6 5 4 3 2 1 0 clkq180deg clkqcalib 0 clkqdelay access rights r r/w r/w dy dy dy dy dy description of the bits bit symbol function 7 clkq180deg if the q-clock is phase shifted more than 180 compared to the i-clock, the bit clkq180deg is set to 1, otherwise it is 0. 6 clkqcalib if this bit is 0, the q-clock is calibrated automatically after the reset phase and after data reception from the card. if this bit is set to 1, no calibration is performed automatically. 5 0 this value shall not be changed 4-0 clkqdelay this register shows the number of delay elements actually used to generate a 90phase shift of the i-clock to obtain the q-clock. it can be written directly by the -processo r or by the automatic calibration cycle.
philips semiconductors product s pecification rev. 3.0; may 2003 multiple protocol contactless reader ic cl rc632 51 confidential 5.2.5 page 4: rf-timing and channel redundancy 5.2.5.1 page register selects the register page. see 5.2.1.1 page register . 5.2.5.2 rxwait register selects the time interval after tr ansmission, before receiver starts. name: rxwait address: 0x21 reset value: 00000101, 0x06 7 6 5 4 3 2 1 0 rxwait access rights r/w r/w r/w r/w r/w r/w r/w r/w description of the bits bit symbol function 7-0 rxwait after data transmission, the ac tivation of the receiver is delayed for rxwait bit- clocks. during this ?frame guard time? any signal at pin rx is ignored.
philips semiconductors product s pecification rev. 3.0; may 2003 multiple protocol contactless reader ic cl rc632 52 confidential 5.2.5.3 channelredundancy register selects kind and mode of checking t he data integrity on the rf-channel. name: channelredundancy address: 0x22 reset value: 00000011, 0x03 7 6 5 4 3 2 1 0 0 0 crc 3309 crc8 rxcrcen txcrcen parityodd parityen access rights r/w r/w r/w r/w r/w r/w r/w r/w description of the bits bit symbol function 7-6 00 this value shall not be changed 5 crc3309 if set to 1, crc-calculation is don e according iso/iec3309 (iso14443b) and iso 15693. note : for usage according to iso14443a this bit has to be 0. for usage according to i ? code 1 this bit has to be 0. 4 crc8 if set to 1, an 8-bit crc is calculated. if set to 0, a 16-bit crc is calculated. 3 rxcrcen if set to 1, the last byte(s) of a re ceived frame is/are interpreted as crc byte/s. if the crc itself is correct the crc byte(s) is/are not passed to the fifo. in case of an error, the crcerr flag is set. if set to 0, no crc is expected. 2 txcrcen if set to 1, a crc is calculated ov er the transmitted data and the crc byte(s) are appended to the data stream. if set to 0, no crc is transmitted. 1 parityodd if set to 1, an odd parity is generated or expected, respectively. if set to 0 an even parity is generat ed or expected, respectively. note : for usage according to iso14443-a this bit has to be 1. 0 parityen if set to 1, a parity bit is inserted in the transmitted data stream after each byte and expected in the received data stream after each byte (mifare ? , iso14443a) if set to 0, no parity bit is inserted or expected (iso14443b)
philips semiconductors product s pecification rev. 3.0; may 2003 multiple protocol contactless reader ic cl rc632 53 confidential 5.2.5.4 crcpresetlsb register lsb of the preset value for the crc register. name: crcpresetlsb address: 0x23 reset value: 01010011, 0x63 7 6 5 4 3 2 1 0 crcpresetlsb access rights r/w r/w r/w r/w r/w r/w r/w r/w description of the bits bit symbol function 7-0 crcpresetlsb crcpresetlsb defines the starting value for cr c-calculation. this value is loaded into the crc at the beginning of transmission, reception and the calccrc command, if the crc calculation is enabled. to use the iso 15693 functionality the crcpresetlsb register has to be set to 0xff.
philips semiconductors product s pecification rev. 3.0; may 2003 multiple protocol contactless reader ic cl rc632 54 confidential 5.2.5.5 crcpresetmsb register msb of the preset value for the crc register. name: crcpresetmsb address: 0x24 reset value: 01010011, 0x63 7 6 5 4 3 2 1 0 crcpresetmsb access rights r/w r/w r/w r/w r/w r/w r/w r/w description of the bits bit symbol function 7-0 crcpresetmsb crcpresetmsb defines the starting value for cr c-calculation. this value is loaded into the crc at the beginning of transmission, reception and the calccrc command, if the crc calculation is enabled. note : this register is not relevant, if crc8 is 1.
philips semiconductors product s pecification rev. 3.0; may 2003 multiple protocol contactless reader ic cl rc632 55 confidential 5.2.5.6 timeslotperiod register defines the time slot period for i ? code1 protocol. name: timeslotperiod address: 0x25 reset value: 00000000, 0x00 7 6 5 4 3 2 1 0 timeslotperiod access rights r/w r/w r/w r/w r/w r/w r/w r/w description of the bits bit symbol function 7-0 timeslotperiod timeslotperiod defines the time between automatically transmitted frames. to send a quit-frame according to the i ? code1 protocol, it is necessary to have a relation to the beginning of the command-frame. the timeslotperiod will start at the end of the command transmission. for detailed information see also chapter 9.2.5
philips semiconductors product s pecification rev. 3.0; may 2003 multiple protocol contactless reader ic cl rc632 56 confidential 5.2.5.7 mfoutselect register selects internal signal applied to pin mfout. name: mfoutselect address: 0x26 reset value:00000000, 0x00 7 6 5 4 3 2 1 0 0 0 0 timeslot period msb 0 mfoutselect access rights r/w r/w r/w r/w r/w r/w r/w r/w description of the bits bit symbol function 7-5 00000 these values shall not be changed 4 timeslotperiod msb msb of value timeslotperiod see register 0x25 3 0 these values shall not be changed mfoutselect defines which signal is routed to pin mfout. 000 constant low 001 constant high 010 modulation signal (envelope) from internal coder, miller coded 011 serial data stream, not miller coded 100 output signal of the energy ca rrier demodulator (card modulation signal) note: only valid mifare ? and iso14443 a at a baudrate of 106 kbaud. 101 output signal of the subcarrier demodulator (manchester coded card signal) note: only valid mifare ? and iso14443 a at a baudrate of 106 kbaud. 110 rfu 2-0 mfoutselect 111 rfu
philips semiconductors product s pecification rev. 3.0; may 2003 multiple protocol contactless reader ic cl rc632 57 confidential 5.2.5.8 preset27 register name: preset27 address: 0x27 reset value: xxxxxxxx, 0xxx 7 6 5 4 3 2 1 0 x x x x x x x x access rights w w w w w w w w
philips semiconductors product s pecification rev. 3.0; may 2003 multiple protocol contactless reader ic cl rc632 58 confidential 5.2.6 page 5: fifo, timer and irq- pin configuration 5.2.6.1 page register selects the register page. see 5.2.1.1 page register . 5.2.6.2 fifolevel register defines the level for fifo under- and overflow warning. name: fifolevel address: 0x29 reset value:00001000, 0x08 7 6 5 4 3 2 1 0 0 0 waterlevel access rights r/w r/w r/w r/w r/w r/w r/w r/w description of the bits bit symbol function 7-6 00 these values shall not be changed 5-0 waterlevel this register defines, the warning level of the cl rc632 for the -processor for a fifo-buffer over- or underflow: hialert is set to 1, if the remaining fifo-buffer space is equal or less than waterlevel bytes in the fifo-buffer. loalert is set to 1, if equal or less than waterlevel bytes are in the fifo-buffer.
philips semiconductors product s pecification rev. 3.0; may 2003 multiple protocol contactless reader ic cl rc632 59 confidential 5.2.6.3 timerclock register selects the divider for the timer clock. name: timerclock address: 0x2a reset value: 00000111, 0x07 7 6 5 4 3 2 1 0 0 0 tautorestart tprescaler access rights r/w r/w r/w r/w r/w r/w r/w r/w description of the bits bit symbol function 7-6 00 these values shall not be changed 5 tautorestart if set to 1, the timer aut omatically restart its count-down from treloadvalue , instead of counting down to zero. if set to 0 the timer decrements to zero and the bit timerirq is set to 1. 4-0 tprescaler defines the timer clock f timer . tprescaler can be adjusted from 0 up to 21. the following formula is used to calculate f timer : f timer = 13.56 mhz / 2 tprescaler .
philips semiconductors product s pecification rev. 3.0; may 2003 multiple protocol contactless reader ic cl rc632 60 confidential 5.2.6.4 timercontrol register selects start and stop conditions for the timer. name: timercontrol address: 0x2b reset value: 00000110, 0x06 7 6 5 4 3 2 1 0 0 0 0 0 tstoprxend tstoprxb egin tstarttxend tstarttxbegin access rights r/w r/w r/w r/w r/w r/w r/w r/w description of the bits bit symbol function 7-4 0000 these values shall not be changed 3 tstoprxend if set to 1, the timer stop s automatically when data reception ends. 0 indicates, that the timer is not influenced by this condition. 2 tstoprxbegin if set to 1, the timer stops automa tically, when the first valid bit is received. 0 indicates, that the timer is not influenced by this condition. 1 tstarttxend if set to 1, the timer starts auto matically when data transmission ends. if the timer is already running, the timer restarts by loading treloadvalue into the timer. 0 indicates, that the timer is not influenced by this condition. 0 tstarttxbegin if set to 1, the timer is starts aut omatically when the first bit is transmitted. if the timer is already running, the timer restarts by loading treloadvalue into the timer. 0 indicates, that the timer is not influenced by this condition.
philips semiconductors product s pecification rev. 3.0; may 2003 multiple protocol contactless reader ic cl rc632 61 confidential 5.2.6.5 timerreload register defines the preset value for the timer. name: timerreload address: 0x2c reset value: 00001010, 0x0a 7 6 5 4 3 2 1 0 treloadvalue access rights r/w r/w r/w r/w r/w r/w r/w r/w description of the bits bit symbol function 7-0 treloadvalue with a start event the timer loads with the treloadvalue . changing this register affects the timer only with the next start event. if treloadvalue is set to 0, the timer cannot start.
philips semiconductors product s pecification rev. 3.0; may 2003 multiple protocol contactless reader ic cl rc632 62 confidential 5.2.6.6 irqpinconfig register configures the output stage for pin irq. name: irqpinconfig address: 0x2d reset value: 00000010, 0x02 7 6 5 4 3 2 1 0 0 0 0 0 0 0 irqinv irqpushpull access rights r/w r/w r/w r/w r/w r/w r/w r/w description of the bits bit symbol function 7-2 000000 these values shall not be changed 1 irqinv if set to 1, the signal on pi n irq is inverted with respect to bit irq . 0 indicates, that the signal on pin irq is equal to bit irq . 0 irqpushpull if set to 1, pin irq works as standard cmos output pad. 0 indicates, that pin irq works as open drain output pad. 5.2.6.7 preset2e name: preset2e address: 0x2e reset value: xxxxxxxx, 0xxx 7 6 5 4 3 2 1 0 x x x x x x x x access rights w w w w w w w w 5.2.6.8 preset2f name: preset2f address: 0x2f reset value: xxxxxxxx, 0xxx 7 6 5 4 3 2 1 0 x x x x x x x x access rights w w w w w w w w
philips semiconductors product s pecification rev. 3.0; may 2003 multiple protocol contactless reader ic cl rc632 63 confidential 5.2.7 page 6: rfu 5.2.7.1 page register selects the register page. see 5.2.1.1 page register . 5.2.7.2 rfu registers name: rfu address: 0x 31, 0x32, 0x33, 0x34, 0x35, 0x36, 037 reset value:xxxxxxxx, 0xxx 7 6 5 4 3 2 1 0 x x x x x x x x access rights r/w r/w r/w r/w r/w r/w r/w r/w note: these registers are reserved for future use.
philips semiconductors product s pecification rev. 3.0; may 2003 multiple protocol contactless reader ic cl rc632 64 confidential 5.2.8 page 7: test control 5.2.8.1 page register selects the register page. see 5.2.1.1 page register . 5.2.8.2 rfu register name: rfu address: 0x39 reset value: xxxxxxxx, 0xxx 7 6 5 4 3 2 1 0 x x x x x x x x access rights w w w w w w w w note: this register is reserved for future use.
philips semiconductors product s pecification rev. 3.0; may 2003 multiple protocol contactless reader ic cl rc632 65 confidential 5.2.8.3 testanaselect register selects analog test signals. name: testanaselect address: 0x3a reset value: 00000000, 0x00 7 6 5 4 3 2 1 0 0 0 0 0 testanaoutsel access rights w w w w w w w w description of the bits bit symbol function 7-4 0000 these values shall not be changed this register selects the internal anal og signal that is routed to pin aux. for detailed information see 21.3 value signal name 3-0 testanaoutsel 0 1 2 3 4 5 6 7 8 9 a b c d e f v mid v bandgap v rxfolli v rxfollq v rxampi v rxampq v corrni v corrnq v corrdi v corrdq v evall v evalr v temp rfu rfu rfu
philips semiconductors product s pecification rev. 3.0; may 2003 multiple protocol contactless reader ic cl rc632 66 confidential 5.2.8.4 rfu register name: rfu address: 0x3b reset value: xxxxxxxx, 0xxx 7 6 5 4 3 2 1 0 x x x x x x x x access rights w w w w w w w w note: this register is reserved for future use. 5.2.8.5 rfu register name: rfu address: 0x3c reset value: xxxxxxxx, 0xxx 7 6 5 4 3 2 1 0 x x x x x x x x access rights w w w w w w w w note: this register is reserved for future use.
philips semiconductors product s pecification rev. 3.0; may 2003 multiple protocol contactless reader ic cl rc632 67 confidential 5.2.8.6 testdigiselect register selects digital test mode. name: testdigiselect address:0x3d reset value: xxxxxxxx, 0xxx 7 6 5 4 3 2 1 0 signalto mfout testdigisignalsel access rights w w w w w w w w description of the bits bit symbol function 7 signaltomfout set to 1, overrules the setting in mfoutselect and the digital test signal defined in testdigisignalsel is routed to pin mfout instead. set to 0, mfoutselect defines the signal delivered at pin mfout. selects the digital test signal to be routed to pin mfout. for detailed information refer to chapter 21.4 testdigisignalsel signal name 6-0 testdigisignalsel f4 hex e4 hex d4 hex c4 hex b5 hex a5 hex 96 hex 83 hex e2 hex s_data s_valid s_coll s_clock rd_sync wr_sync int_clock bpsk_out bpsk_sig 5.2.8.7 rfu registers name: rfu address: 0x3e, 0x3f reset value: xxxxxxxx, 0xxx 7 6 5 4 3 2 1 0 x x x x x x x x access rights w w w w w w w w note: these registers are reserved for future use.
philips semiconductors product s pecification rev. 3.0; may 2003 multiple protocol contactless reader ic cl rc632 68 confidential 5.3 cl rc632 register flags overview flag(s) register address register, bit position accesserr errorflag 0x0a, bit 5 bitphase bitphase 0x1b, bits 7:0 charspacing typebframing 0x17, bits 4:2 clkq180deg clockqcontrol 0x1f, bit 7 clkqcalib clockqcontrol 0x1f, bit 6 clkqdelay clockqcontrol 0x1f, bits 4:0 coderrate codercontrol 0x14, bits 5:3 collerr errorflag 0x0a, bit 0 colllevel rxthreshold 0x1c, bits 3:0 collpos collpos 0x0b, bits 7:0 command command 0x01, bits 5:0 crc3309 channelredundancy 0x22, bit 5 crc8 channelredundancy 0x22, bit 4 crcerr errorflag 0x0a, bit 3 crcpresetlsb crcpresetlsb 0x23, bits 7:0 crcpresetmsb crcpresetmsb 0x24, bits 7:0 crcready secondarystatus 0x05 , bit 5 crcresultmsb crcresultmsb 0x0e, bits 7:0 crcresultlsb crcresul tlsb 0x0d, bits 7:0 crypto1on control 0x09, bit 3 decodersource rxcontrol2 0x1e, bits 1:0 e2ready secondarystatus 0x05, bit 6 eofwidth typebframing 0x17, bit 5 err primarystatus 0x03, bit 2 fifodata fifodata 0x02, bits 7:0 fifolength fifolength 0x04, bits 7:0 fifoovfl errorflag 0x0a, bit 4 filterampdet bpskdemcontrol 0x1d, bit 4 flushfifo control 0x09, bit 0 force100ask txcontrol 0x11, bit 4 framingerr errorflag 0x0a, bit 2 gain rxcontrol1 0x19, bits 1:0 gscfgcw cwconductance 0x12, bits 5:0
philips semiconductors product s pecification rev. 3.0; may 2003 multiple protocol contactless reader ic cl rc632 69 confidential flag(s) register address register, bit position gscfgmod modconductance 0x13, bits 5:0 hialert primarystatus 0x03, bit 1 hialertien interrupten 0x06, bit 1 hialertirq interruptrq 0x07, bit 1 idleien interrupten 0x06, bit 2 idleirq interruptrq 0x07, bit 2 ifdetectbusy command 0x01, bit 7 irq primarystatus 0x03, bit 3 irqinv irqpinconfig 0x2d, bit 1 irqpushpull irqpinconfig 0x2d, bit 0 iso selection rxcontrol1 0x19, bits 4:3 keyerr errorflag 0x0a, bit 6 loalert primarystatus 0x03, bit 0 loalertien interrupten 0x06, bit 0 loalertirq interruptrq 0x07, bit 0 lpoff rxcontrol1 0x19, bit 2 mfoutselect mfoutselect 0x26, bits 2:0 minlevel rxthreshold 0x1c, bits 7:4 modemstate primarystatus 0x03 , bit 6:4 modulatorsource txcontrol 0x11, bits 6:5 modwidth modwidth 0x15, bits 7:0 norxegt bpskdemcontrol 0x1d, bit 6 norxeof bpskdemcontrol 0x1d, bit 5 norxsof bpskdemcontrol 0x1d, bit 7 notxeof typebframing 0x17, bit 6 notxsof typebframing 0x17, bit 7 pageselect page 0x00, 0x08, 0x10, 0x18, 0x20, 0x28, 0x30, 0x38, bits 2:0 parityen channelredundancy 0x22, bit 0 parityerr errorflag 0x0a, bit 1 parityodd channelredundancy 0x22 , bit 1 powerdown control 0x09, bit4 rcvclkseli rxcontrol2 0x1e, bit 7 rxalign bitframing 0x0f, bits 6:4
philips semiconductors product s pecification rev. 3.0; may 2003 multiple protocol contactless reader ic cl rc632 70 confidential flag(s) register address register, bit position rxautopd rxcontrol2 0x1e, bit 6 rxcrcen channelredundancy 0x22, bit 3 rxcoding decodercontrol 0x1a, bit 0 rxframing decodercontrol 0x1a, bits 4:3 rxien interrupten 0x06, bit 3 rxirq interruptrq 0x07, bit 3 rxlastbits secondarystatus 0x05, bits 2:0 rxmultiple decodercontrol 0x1a,bit 6 rxwait rxwait 0x21, bits 7:0 setien interrupten 0x06, bit 67 setirq interruptrq 0x07, bit 7 signaltomfout testdigiselect 0x3d, bit 7 sofwidth typebframing 0x17, bits 1:0 standby control 0x09, bit 5 subcpulses rxcontrol1 0x19, bits 7:5 taub bpskdemcontrol 0x1d, bits 1:0 taud bpskdemcontrol 0x1d, bits 3:2 tautorestart timerclock 0x2a, bit 5 testanaoutsel testanaselect 0x3a, bits 6:4 testdigisignalsel testdigiselect 0x3d, bit 6:0 timerien interrupten 0x06, bit 5 timerirq interruptrq 0x07, bit 5 timervalue timervalue 0x0c, bits 7:0 timeslotperiod timeslotperiod 0x25, bits 7:0 timeslotperiodmsb mfoutselect 0x26, bit 4 tprescaler timerclock 0x2a, bits 4:0 treloadvalue timerreload 0x2c, bits 7:0 trunning secondarystatus 0x05, bit 7 tstarttxbegin timercontrol 0x2b, bit 0 tstarttxend timercontrol 0x2b, bit 1 tstartnow control 0x09, bit 1 tstoprxbegin timercontrol 0x2b, bit 2 tstoprxend timercontrol 0x2b, bit 3 tstopnow control 0x09, bit 2
philips semiconductors product s pecification rev. 3.0; may 2003 multiple protocol contactless reader ic cl rc632 71 confidential flag(s) register address register, bit position tx1rfen txcontrol 0x11, bit 0 tx2cw txcontrol 0x11, bit 3 tx2inv txcontrol 0x11, bit 3 tx2rfen txcontrol 0x11, bit 1 txcoding codercontrol 0x14, bits 2:0 txcrcen channelredundancy 0x22, bit 2 txien interrupten 0x06, bit 4 txirq interruptrq 0x07, bit 4 txlastbits bitframing 0x0f, bits 2:0 usepageselect page 0x00, 0x08, 0x10, 0x18, 0x20, 0x28, 0x30, 0x38, bit 7 waterlevel fifolevel 0x29, bits 5:0 zeroaftercoll decodercontrol 0x1a, bit 5
philips semiconductors product s pecification rev. 3.0; may 2003 multiple protocol contactless reader ic cl rc632 72 confidential 5.4 modes of register addressing three mechanisms are valid to operate with the cl rc632: ? initiating functions and controlli ng data manipulation by executing commands ? configuring electrical and functional behaviour via a set of configuration bits ? monitoring the state of the cl rc632 by reading status flags the commands, configuration bits and flags are accessed via the -processor interface. the cl rc632 can internally address 64 register s. this basically requires six address lines. 5.4.1 paging mechanism the cl rc632 register set is segmented into 8 pages with 8 register each. the page-register can always be addressed, no matter which page is currently selected. 5.4.2 dedicated address bus using the cl rc632 with dedicated address bus, t he -processor defines three address lines via the address pins a0, a1, and a2. this allows addressing with in a page. to switch between registers in different pages the paging mechanism needs then to be used. the following table shows how the register address is assembled: register bit: usepageselect register-address 1 pageselect2 pageselect1 pageselect0 a2 a1 a0 table 5-3: dedicated address bus: assembling the register address 5.4.3 multiplexed address bus using the cl rc632 with multiplexed address bus, t he -processor may define all 6 address lines at once. in this case either the paging mechanism or linear addressing may be used. the following table shows how the register address is assembled: interface bus type register bit: usepageselect register-address multiplexed address bus (paging mode) 1 pageselect2 pageselect1 pageselect0 ad2 ad1 ad0 multiplexed address bus (linear addressing) 0 ad5 ad4 ad3 ad2 ad1 ad0 table 5-4: multiplexed address bus: assembling the register address
philips semiconductors product s pecification rev. 3.0; may 2003 multiple protocol contactless reader ic cl rc632 73 confidential 6 memory organisation of the e2prom 6.1 diagram of the e2prom memory organisation block number block address byte addresses access rights memory content see also 0 0 00 ? 0f r product information field 6.2 1 1 10 ? 1f r/w 2 2 20 ? 2f r/w start up register initialisation file 6.3.1 3 3 30 ? 3f r/w 4 4 40 ? 4f r/w 5 5 50 ? 5f r/w 6 6 60 ? 6f r/w 7 7 70 ? 7f r/w register initialisation file for user data or second initialisation 6.3.3 8 8 80 ? 8f w 9 9 90 ? 9f w 10 a a0 ? af w 11 b b0 ? bf w 12 c c0 ? cf w 13 d d0 ? df w 14 e e0 ? ef w 15 f f0 ? ff w 16 10 100 ? 10f w 17 11 110 ? 11f w 18 12 120 ? 12f w 19 13 130 ? 13f w 20 14 140 ? 14f w 21 15 150 ? 15f w 22 16 160 ? 16f w 23 17 170 ? 17f w 24 18 180 ? 18f w 25 19 190 ? 19f w 26 1a 1a0 ? 1af w 27 1b 1b0 ? 1bf w 28 1c 1c0 ? 1cf w 29 1d 1d0 ? 1df w 30 1e 1e0 ? 1ef w 31 1f 1f0 ? 1ff w keys for crypto1 6.4 table 6-1: diagram of e2prom memory organisation
philips semiconductors product s pecification rev. 3.0; may 2003 multiple protocol contactless reader ic cl rc632 74 confidential 6.2 product information field (read only) byte 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 meaning product type identificatio n rfu product serial number internal rsmaxp crc table 6-2: product information field product type identification: the cl rc632 is a member of a new family for highl y integrated reader ic?s. each member of the product family has its unique product type identification. the va lue of the product type ident ification is shown in the table below: product type identification byte 0 1 2 3 4 value 30 hex ff hex ff hex 0f hex xx hex table 6-3: product type identification definition byte 4 indicates the current version number. product serial number: the cl rc632 holds a four byte serial number that is unique for each device. internal: these 2 bytes hold internal trimming parameters. rsmaxp: maximum source resistance for the p-chann el driver transistor of pin tx1 and tx2 the source resistance of the p-channel driver tran sistors of pin tx1 and tx2 may be adjusted via the value gscfgcw in the cwconductance register (see chapter 13.3). the mean value of the maximum adjustable source resistance of the pins tx1 and tx2 is stor ed as an integer value in ohms in byte rsmaxp. this value is denoted as maximum adjustable source resistance rs ref,max,p and is measured setting gscfgcw in the register cwconductance to 01 hex . it is in the range between about 80 to 120 ohm. crc: the content of the product information field is secu red via a crc-byte, which is checked during start up.
philips semiconductors product s pecification rev. 3.0; may 2003 multiple protocol contactless reader ic cl rc632 75 confidential 6.3 register initialisat ion files (read/write) register initialisation in the register address range from 10 hex to 2f hex is done automatically during the initialising phase (see 11.3), using the start up register initialisation file. furthermore, the user may initialise the cl rc632 regist ers with values from the register initialisation file executing the loadconfig-command (see 18.7.1). notes: ? the page-register (addressed with 10 hex , 18 hex , 20 hex , 28 hex ) is skipped and not initialised. ? make sure, that all preset registers are not changed. ? make sure, that all register bits that are reserved for future use (rfu) are set to 0. 6.3.1 start up register initialisation file (read/write) the content of the e2prom memory bock address 1 and 2 are used to initialise the cl rc632 registers 10 hex to 2f hex during the initialising phase automatically. the default values written into the e2prom during production are shown chapter 6.3.2. the assignment is the following: e2prom byte address register address remark 10 hex (block 1, byte 0) 10 hex skipped 11 hex 11 hex copied ? ? ? 2f hex (block 2, byte 15) 2f hex copied table 6-4: byte assignment for register initialisation at start up
philips semiconductors product s pecification rev. 3.0; may 2003 multiple protocol contactless reader ic cl rc632 76 confidential 6.3.2 shipment content of start up register initialisation file during production test, the start up register initialisation file is initialised with the values shown in the table below. with each power up these values are written in to the cl rc632 register during the initialising phase. e2prom byte address reg. address value description 10 10 00 page : free for user 11 11 58 txcontrol: transmitter pins tx1 and tx2 switc hed off, bridge driver configuration, modulator driven from in ternal digital circuitry 12 12 3f cwconductance: source resistance of tx1 and tx2 to minimum. 13 13 3f modconductance: defines the output conductance 14 14 19 codercontrol: iso14443-a coding is set 15 15 13 modwidth : pulse width for miller pulse coding is set to standard configuration. 16 16 3f modwithsof: pulse width of sof 17 17 3b typeframing: iso 14443-a framing is set 18 18 00 page: free for user 19 19 73 rxcontrol1: iso 14443-a is set and internal amplifier gain is maximum. 1a 1a 08 decodercontrol: a bit-collision always evaluates to high in the data bit stream. 1b 1b ad bitphase: bitphase is set to standard configuration. 1c 1c ff rxthreshold: minlevel and colllevel are set to maximum. 1d 1d 1e bpskdemcontrol: iso14443-a is set 1e 1e 41 rxcontrol2: use q-clock for the receiver, ?autom atic receiver off? is switched on, decoder is driven from inte rnal analog circuitry. 1f 1f 00 clockqcontrol: ?automatic q-clock calibration? is switched on. 20 20 00 page: free for user 21 21 06 rxwait : frame guard time is set to six bit clocks. 22 22 03 channelredundancy: channel redundancy is set according to iso14443-a. 23 23 63 crcpresetlsb: crc-preset value is set according to iso14443-a. 24 24 63 crcpresetmsb: crc-preset value is set according to iso14443-a. 25 25 00 timeslotperiod: : defines the time for the i code1 time slots 26 26 00 mfoutselect: pin mfout is set to low. 27 27 00 preset27 28 28 00 page: free for user 29 29 08 fifolevel : waterlevel fifo buffer warning level is set to standard configuration. 2a 2a 07 timerclock: tprescaler is set to standard configuration, time r unit restart function is switched off. 2b 2b 06 timercontrol: timer is started at the end of transmissi on, stopped at the beginning of reception. 2c 2c 0a timerreload: treloadvalue: the timer unit preset value is set to standard configuration. 2d 2d 02 irqpinconfig: pin irq is set to high impedance. 2e 2e 00 preset2e 2f 2f 00 preset2f table 6-5: shipment content of start up configuration file note: the default configuration of the cl rc632 supports the mifare ? and iso 14443 a communication scheme. the memory addresses 3 to 7 may be used for user specific in itialisation files as i code1, iso15693 or iso14443 b.
philips semiconductors product s pecification rev. 3.0; may 2003 multiple protocol contactless reader ic cl rc632 77 confidential 6.3.3 register initialisation file (read/write) the content of the e2prom memory from block addr ess 3 to 7 may be used to initialise the cl rc632 registers 10 hex to 2f hex by execution of the loadconfig-command (see 18.7.1). it requires a two bytes argument, used as the two bytes long e2prom starti ng byte address for the initialisation procedure. the assignment is the following: e2prom byte address register address remark starting byte address for the e2prom 10 hex skipped starting byte address for the e2prom +1 11 hex copied ? ? ? starting byte address for the e2prom + 31 2f hex copied table 6-6: byte assignment for register initialisation at start up the register initialisation file is big enough to hold th e values for two initialisation sets and leaves one more block (16 bytes) for the user. note: the register initialisation file is read- and write- able for the user. therefore, these bytes may also be used to store user specific data for other purposes. the standard configuration for the cl rc632 enables the mifare? and iso14443 setting after each power up. to give the user the needed flexibility the star tup configuration might be adapted and for example the icode1 start up configuration might be stored in the register block address 3 and 4.
philips semiconductors product s pecification rev. 3.0; may 2003 multiple protocol contactless reader ic cl rc632 78 confidential 6.3.4 content of i code1 and iso15693 start up register values to enable the i code1 functionality the following table gives an overview on the start up values for communication according t to the i code1 and iso15693 scheme e2prom byte address reg. address value description 30 10 00 page : free for user 31 11 58 txcontrol: transmitter pins tx1 and tx2 switc hed off, bridge driver configuration, modulator driven from in ternal digital circuitry 32 12 3f cwconductance: source resistance of tx1 and tx2 to minimum. 33 13 05 modgscfg: source resistance of tx1 and tx2 at the time of modulation, to determine the modulation index 34 14 2c codercontrol: selects the bit coding mode and the framing during transmission 35 15 3f modwidth : pulse width for ?used code (1 out of 256, rz or 1 out of 4)? pulse coding is set to standard configuration. 36 16 3f modwidthsof pulse width of sof 37 17 00 typebframing 38 18 00 page: free for user 39 19 8b rxcontrol1: amplifier gain is maximum. 3a 1a 00 decodercontrol: a bit-collision always evaluates to high in the data bit stream. 3b 1b 54 bitphase: bitphase is set to standard configuration. 3c 1c 68 rxthreshold: minlevel and colllevel are set to maximum. 3d 1d 00 bpskdemcontrol 3e 1e 41 rxcontrol2: use q-clock for the receiver, ?autom atic receiver off? is switched on, decoder is driven from inte rnal analog circuitry. 3f 1f 00 clockqcontrol: automatic q-clock calibration? is switched on. 40 20 00 page: free for user 41 21 08 rxwait : frame guard time is set to six bit clocks. 42 22 0c channelredundancy: channel redundancy is set according to i code1. 43 23 fe crcpresetlsb: crc-preset value is set according to i code1. 44 24 ff crcpresetmsb: crc-preset value is set according to i code1. 45 25 00 timeslot period : defines the time for the i code1 time slots 46 26 00 mfoutselect: pin mfout is set to low. 47 27 00 preset27 48 28 00 page: free for user 49 29 3e fifolevel: waterlevel : fifo buffer warning level is set to standard configuration. 4a 2a 0b timerclock: tprescaler is set to standard configuration, time r unit restart function is switched off. 4b 2b 02 timercontrol: timer is started at the end of transmissi on, stopped at the beginning of reception. 4c 2c 00 timerreload: treloadvalue: the timer unit preset value is set to standard configuration 4d 2d 02 irqpinconfig: pin irq is set to high impedance. 4e 2e 00 preset2e 4f 2f 00 preset2f table 6-7: content of i code1 start up configuration 6.4 crypto1 keys (write only) the mifare ? classic security requires specific keys to encrypt the communication on the contactless interface. these keys are named as crypto1 keys.
philips semiconductors product s pecification rev. 3.0; may 2003 multiple protocol contactless reader ic cl rc632 79 confidential 6.4.1 key format to store a key in the e2prom, it has to be written in a specific format. each key byte has to be split into the lower four bits k0 to k3 (lower nibble) and the higher f our bits k4 to k7 (higher nibble). each nibble is stored twice in one byte and one of the two nibbles is bit-wise inverted. this format is a precondition for successful execution of the loadkeye2- (see 18.9.1) and the loadkey-command (see 18.9.2). with this format, 12 bytes of the e2prom me mory are needed to store a 6 byte long key. this is shown in the following table: example: for the actual key a0 a1 a2 a3 a4 a5 hex the value 5a f0 5a e1 5a d2 5a c3 5a b4 5a a5 hex must be written into the e2prom. note: although it is possible to load data of any other form at into the key storage location of the e2prom, it is not possible to obtain a valid card authentication with such a key. the loadkeye2-command (see 18.9.1) will fail. 6.4.2 storage of keys in the e2prom the cl rc632 reserves 384 bytes of memory area in the e2prom to hold crypto1 keys. it uses no memory segmentation to mirror the 12 bytes structure of key st orage. thus, every byte of the dedicated memory area may be the start of a key. example: if a key loading cycle starts at the last byte address of an e2prom block, e.g. key byte 0 is stored at 12f hex , the following bytes are stored in the next e2pr om block , e.g. key byte 1 is stored at 130 hex , byte 2 at 131 hex , up to byte 11 at 13a hex . with 384 bytes of memory and 12 bytes needed for one key, 32 different keys may be stored in the e2prom. note: it is not possible to load a key exceeding the e2prom byte location 1ff hex . 0 (lsb) 1 5 (msb) n n+1 n+2 n+3 n+10 n+11 5a hex f0 hex 5a hex e1 hex 5a hex a5 hex master key byte master key bits e2prom byte address example k3 k2 k1 k0 k3 k2 k1 k0 k3 k2 k1 k0 k3 k2 k1 k0 k3 k2 k1 k0 k3 k2 k1 k0 k7 k6 k5 k4 k7 k6 k5 k4 k7 k6 k5 k4 k7 k6 k5 k4 k7 k6 k5 k4 k7 k6 k5 k4 table 6-8: key storage format
philips semiconductors product s pecification rev. 3.0; may 2003 multiple protocol contactless reader ic cl rc632 80 confidential 7 fifo buffer 7.1 overview an 8x64 bit fifo buffer is implemented in the cl rc632 acting as a parallel-to-par allel converter. it buffers the input and output data stream between the -processor and the internals of the cl rc632. thus, it is possible to handle data streams with lengths of up to 64 bytes without taking timing constraints into account. 7.2 accessing the fifo buffer 7.2.1 access rules the fifo-buffer input and output data bus is connected to the fifodata register . writing to this register stores one byte in the fifo-buffer and increments the internal fifo-buffer write-pointer. reading from this register shows the fifo-buffer contents stored at t he fifo-buffer read-pointer and increments the fifo- buffer read-pointer. the distance between the writ e- and read-pointer can be obtained by reading the fifolength register . when the -processor starts a command, the cl rc632 may, while the command is in progress, access the fifo-buffer according to that command. physically onl y one fifo-buffer is implemented, which can be used in input- and output direction. theref ore the -processor has to take care, not to access the fifo-buffer in an unintended way. the following table gives an overview on fifo access during command processing: -processor is allowed to active command write to fifo read from fifo remark startup - - idle - - transmit - receive - transceive -processor has to know the actual state of the command (transmitting or receiving) writee2 - reade2 the -processor has to prepare the arguments, afterwards only reading is allowed loadkeye2 - loadkey - authent1 - authent2 - - loadconfig - calccrc - table 7-1: allowed access to the fifo-buffer
philips semiconductors product s pecification rev. 3.0; may 2003 multiple protocol contactless reader ic cl rc632 81 confidential 7.3 controlling the fifo-buffer besides writing to and reading from the fifo-buffer, t he fifo-buffer pointers might be reset by setting the bit flushfifo . consequently, fifolength becomes zero, fifoovfl is cleared, the actua lly stored bytes are not accessible anymore and the fifo-buffer c an be filled with another 64 bytes again. 7.4 status information about the fifo-buffer the -processor may obtain the following data about the fifo-buffers status: ? number of bytes already stored in the fifo-buffer: fifolength ? warning, that the fifo-buffer is quite full: hialert ? warning, that the fifo-buffer is quite empty: loalert ? indication, that bytes were written to th e fifo-buffer although it was already full: fifoovfl fifoovfl can be cleared only by setting bit flushfifo . the cl rc632 can generate an interrupt signal ? if loalertirq is set to 1 it will activate pin irq when loalert changes to 1. ? if hialertirq is set to 1 it will activate pin irq when hialert changes to 1. the flag hialert is set to 1 if only waterlevel bytes or less can be stored in the fifo-buffer. it is generated by the following equation: waterlevel fifolength hialert ? = ) 64 ( the flag loalert is set to 1 if waterlevel bytes or less are actually stored in the fifo-buffer. it is generated by the following equation: waterlevel fifolength loalert =
philips semiconductors product s pecification rev. 3.0; may 2003 multiple protocol contactless reader ic cl rc632 82 confidential 7.5 register overview fifo buffer the following table shows the related flags of the fifo buffer in alphabetic order. flags register address register, bit position fifolength fifolength 0x04, bits 6-0 fifoovfl errorflag 0x0a, bit 4 flushfifo control 0x09, bit 0 hialert primarystatus 0x03, bit 1 hialertien interruptien 0x06, bit 1 hialertirq interruptirq 0x07, bit 1 loalert primarystatus 0x03, bit 0 loalertien interruptien 0x06, bit 0 loalertirq interruptirq 0x07, bit 0 waterlevel fifolevel 0x29, bits 5-0 table 7-2. registers associated with the fifo buffer
philips semiconductors product s pecification rev. 3.0; may 2003 multiple protocol contactless reader ic cl rc632 83 confidential 8 interrupt request system 8.1 overview the cl rc632 indicates certain events by setting bit irq in the primarystatus-register and, in addition, by activating pin irq. the signal on pin irq may be used to interrupt the -processor using its interrupt handling capabilities. this allows the implem entation of efficient -processor software. 8.1.1 interrupt sources overview the following table shows the integrat ed interrupt flags, the related source and the condition for its setting. the interrupt flag timerirq indicates an interrupt set by the timer unit. the setting is done when the timer decrements from 1 either down to zero ( tautorestart flag disabled ) or to the tpreload value if tautorestart is enabled. the txirq bit indicates interrupts from different sources. if the transmitter is active and the state changes from sending data to transmitting the end of frame pattern , the transmitter unit sets automatically the interrupt bit. the crc coprocessor sets txirq after having processed all data from the fifo buffer. this is indicated by the flag crcready = 1. if the e 2 prom programming has finished the txirq bit is set, indicated by the bit e2ready = 1. the rxirq flag indicates an interrupt when the end of the received data is detected. the flag idleirq is set if a command finishes and the content of the command register changes to idle. the flag hialertirq is set to 1 if the hialert bit is set to one, that means t he fifo buffer has reached the level indicated by the bit waterlevel , see chapter 7.4. the flag loalertirq is set to 1 if the loalert bit is set to one, that mean s the fifo buffer has reached the level indicated by the bit waterlevel , see chapter 7.4. interrupt flag interrupt sour ce is set automatically, when timerirq timer unit the timer counts from 1 to 0 transmitter a data stream, transmitted to the card, ends crc-coprocessor all data from the fifo buffer has been processed txirq e2prom all data from the fifo buffer has been programmed rxirq receiver a data stream, received from the card, ends idleirq command register a command execution finishes hialertirq fifo-buffer the fifo-buffer is getting full loalertirq fifo-buffer the fifo-buffer is getting empty table 8-1: interrupt sources
philips semiconductors product s pecification rev. 3.0; may 2003 multiple protocol contactless reader ic cl rc632 84 confidential 8.2 implementation of interrupt request handling 8.2.1 controlling interrupts and their status the cl rc632 informs the -processor about the interrupt request source by setting the according bit in the interruptrq register . the relevance of each interrupt request bi t as source for an interrupt may be masked with the interrupt enable bits of the interrupten register . register bit 7 bit 6 bit 5 bi t 4 bit 3 bit 2 bit 1 bit 0 interrupten setien rfu timerien txien rxien idleien hialertien loalertien interruptrq setirq rfu timerirq txir q rxirq idleirq hialertirq loalertirq table 8-2: interrupt control registers if any interrupt request flag is set to 1 (showing that an interrupt request is pending) and the corresponding interrupt enable flag is set the status flag irq in the primarystatus register is set to 1. furthermore different interrupt sources can be set active simultaneously. t herefore, all interrupt request bits are ?or?ed and connected to the flag irq and forwarded to pin irq. 8.2.2 accessing the interrupt registers the interrupt request bits are set automatically by the internal state machines of the cl rc632. additionally the -processor has access in or der to set or to clear them. a special implementation of the interruptrq and the interrupten register allows the change a single bit status without influencing the other ones. if a specif ic interrupt register shall be set to one, the bit setixx has to be set to 1 and simultaneously the specific bit has to be set to 1 too. vice versa, if a specific interrupt flag shall be cleared, a zero has to be written to the setixx and simultaneously the specific address of the interrupt register has to be set to 1. if a bit cont ent shall not be changed during the setting or clearing phase a zero has to be written to the specific bit location. example: writing 3f hex to the interruptrq register clears all bits as setirq in this case is set to 0 and all other bits are set to 1. writing 81 hex sets bit loalertirq to 1 and leaves all other bits untouched. 8.3 configuration of pin irq the logic level of the status flag irq is visible at pin irq. in addition, the signal on pin irq may be controlled by the following bits of the irqpinconfig register : ? irqinv : if set to 0, the signal on pin irq is equal to the logic level of bit irq . if set to 1, the signal on pin irq is inverted with respect to bit irq . ? irqpushpull : if set to 1, pin irq has sta ndard cmos output characteristics otherwise it is an open drain output and an external resist or is necessary to achieve a high level at this pin. note: during the reset phase (see 11.2) irqinv is set to 1 and irqpushpull to 0. this results in a high impedance at pin irq.
philips semiconductors product s pecification rev. 3.0; may 2003 multiple protocol contactless reader ic cl rc632 85 confidential 8.4 register overview interrupt request system the following table shows the related flags of t he interrupt request system in alphabetic order. flags register address register, bit position hialertien interrupten 0x06, bit 1 hialertirq interruptrq 0x07, bit 1 idleien interrupten 0x06, bit 2 idleirq interruptrq 0x07, bit 2 irq primarystatus 0x03, bit 3 irqinv irqpinconfig 0x07, bit 1 irqpushpull irqpinconfig 0x07, bit 0 loalertien interrupten 0x06, bit 0 loalertirq interruptrq 0x07, bit 0 rxien interrupten 0x06, bit 3 rxirq interruptrq 0x07, bit 3 setien interrupten 0x06, bit 7 setirq interruptrq 0x07, bit 7 timerien interrupten 0x06, bit 5 timerirq interruptrq 0x07, bit 5 txien interrupten 0x06, bit 4 txirq interruptrq 0x07, bit 4 table 8-3 registers associated with the interrupt request system
philips semiconductors product s pecification rev. 3.0; may 2003 multiple protocol contactless reader ic cl rc632 86 confidential 9 timer unit 9.1 overview a timer is implemented in the cl rc632. it derives it s clock from the 13.56 mhz chip-clock. the -processor may use this timer to manage timing relevant tasks. the timer unit may be used in one of the following configurations: ? timeout-counter ? watch-dog counter ? stop watch ? programmable one-shot ? periodical trigger the timer unit can be used to measure the time interval between two events or to indicate that a specific event occurred after a specific time. the timer ca n be triggered by events which will be explained in the following, but the timer itself does not influence any in ternal event (e.g. a timeout during data receiving does not influence the receiving process automatically). fu rthermore, several timer related flags are set and these flags can be used to generate an interrupt.
philips semiconductors product s pecification rev. 3.0; may 2003 multiple protocol contactless reader ic cl rc632 87 confidential 9.2 implementation of the timer unit 9.2.1 block diagram the following block diagram shows the timer module. the timer unit is designed in a way, that several event s in combination with enabling flags start or stop the counter. for example, setting the bit tstarttxbegin to 1 enables to control the receiving of data using the timer unit. in addition, the first received bit is indicated by txbeginevent . this combination starts the counter at the defined treloadvalue . the timer stops either automatically if the counter val ue is equal to zero, or if a defined stop event happens. counter module (x <= x-1) start counter / parallel load stop counter >clock clock divider 13.56 mhz tprescaler [4:0] treloadvalue [7:0] tstopnow rxend event tautorestart tstoprxend rxbegin event tstoprxbegin tstartnow txend event tstarttxend txbegin event tstarttxbegin timervalue [7:0] parallel in parallel out counter = 0 ? to interrupt logic: timerirq to parallel interface s r q q trunning figure 9-1: timer module block diagram
philips semiconductors product s pecification rev. 3.0; may 2003 multiple protocol contactless reader ic cl rc632 88 confidential 9.2.2 controlling the timer unit the main part of the timer unit is a down-counter. as long as the down-counter value is unequal zero, it decrements its value with each timer clock. if tautorestart is enabled the timer does not decrement down to zero. having reached the value 1 the timer reloads with the next clock with the timerreload value. the timer is started immediately by loading a value from the timerreload register into the counter module. this may be triggered by one of the following events: ? transmission of the first bit to the card (txbegin event) and bit tstarttxbegin is 1 ? transmission of the last bit to the card (txend event) and bit tstarttxend is 1 ? bit tstartnow is set to 1 (by the -processor) note: every start event reloads the timer from the timerreload register . thus, the timer unit is re-triggered. the timer can be configured to stop with one of the following events: ? reception of the first valid bit from the card (rxbegin event) and bit tstoprxbegin is set to 1 ? reception of the last bit from the card (rxend event) and bit tstoprxend is set to 1 ? the counter module has decrement down to zero and bit tautorestart is set to 0 ? bit tstopnow is set to 1 (by the -processor) loading a new value, e.g. zero, into the timerreload register does not immediately influence the counter, since the timerreload register affects the counter units content only with the next start event. thus, the timerreload register may be changed even if the timer unit is already counting. the consequence of changing the timerreload register will be visible a fter the next start event. if the counter is stopped by setting bit tstopnow, no timerirq is signalled. 9.2.3 timer unit clock and period the clock of the timer unit is derived from the 13.56 mhz chip clock via a programmable divider. the clock selection is done with the tprescaler register that defines the timer uni t clock frequency according to the following formula: mhz f t escaler t timerclock timerclock 56 . 13 2 1 pr = = the possible values for the tprescaler register range from 0 up to 21 resulting in minimum time t timerclock of about 74 ns up to about 150 ms. the time period elapsed since the last start event is calculated with timerclock timer f timervalue ue treloadval t ? = resulting in a minimum time t timer of about 74 ns up to about 40 s.
philips semiconductors product s pecification rev. 3.0; may 2003 multiple protocol contactless reader ic cl rc632 89 confidential 9.2.4 status of the timer unit the trunning bit in the secondarystatus register shows the timer?s curr ent status. any configured start event starts the timer at the treloadvalue and changes the status flag trunning to 1, any configured stop event stops the timer and sets the status flag trunning back to 0. as long as status flag trunning is set to 1, the timervalue register changes with the next timer unit clock. the actual timer unit content can be read directly via the timervalue register . 9.2.5 timeslotperiod for sending of i?code1-quit-frames it is necessary to generat a exact chronological relation to the begin of the command frame. is timeslotperiod > 0, with the end of command tran smission the timeslotperiod starst. if there are data in the fifo after reaching the end of ti meslotperiod, these data were sent at that moment. if the fifo is empty nothing happens. as long as the contend of timeslotperiod is > 0 the counter for the timeslotperiod will start automatically after reaching the end. this allows a exact time relation to the end (as well as to the beginning) of the command frame for the generation and sending of the i ? code1-quit-frames is timeslotperiod > 0 the next frame starts exact with the interval timeslotperiod/coderrate delayed after each previous send frame. coderr ate defines the clock frequency of the coder. if timeslotperiod = 0, the send function will not be triggered automatically. the content of the register timeslotperiod can be ch anged during the active mode. the modification take effect at the next restart of the timeslotperiod.
philips semiconductors product s pecification rev. 3.0; may 2003 multiple protocol contactless reader ic cl rc632 90 confidential example: coderrate = 0x05 (~52.97khz) for i ? code1 standard mode the interval should be 8.458ms ->timeslotperiod = coderrate * interval = 52.97khz * 8.458ms ?1 = 447 (447 = 0x1bf) note: the msb of the timeslotperiod is in the mfoutselect register. command quit1 quit2 response1 response2 tsp1 tsp2 command quit1 quit2 response1 response2 tsp1 tsp2 timeslotperiod for tsp1 timeslotperiod for tsp2 i ? code1 standard mode 0xbf 0x1bf i ? code1 fast mode 0x5f 0x67 note: it is strictly recommended that bit txcrcen is se t to 0 before the quit-frame is sent. if the txcrcen is not set to 0 a crc value is calculated and sent with the quit-frame. to calculate the quit value a crc8 algorithm has to be used. 9.3 usage of the timer unit 9.3.1 time-out- and watch-dog-counter having started the timer by setting treloadvalue the timer unit decrements the timervalue register beginning with a certain start event. if a certain stop event occurs e.g. a bit is received from the card, the timer unit stops (no interrupt is generated). on the other hand, if no stop event occu rs, e.g. the card does not answer in the expected time, the timer unit decrements down to zero and generates a timer inte rrupt request. this signals the -processor that the expected event has not occurred in the given time t timer .
philips semiconductors product s pecification rev. 3.0; may 2003 multiple protocol contactless reader ic cl rc632 91 confidential 9.3.2 stop watch the time t timer between a certain start- and stop event may be measured by the -processor by means of the cl rc632 timer unit. setting treloadvalue the timer starts to decrement. if the defined stop event occurs the timers stops. the time between start and stop can be calculated by () timer value value t timer load t t * re ? = ? if the timer does not decrements down to zero. 9.3.3 programmable one-shot timer the -processor starts the timer unit and waits fo r the timer interrupt. after the specified time t timer the interrupt will occur. 9.3.4 periodical trigger if the -processor sets bit tautorestart , it will generate an interrupt request periodically after every t timer .
philips semiconductors product s pecification rev. 3.0; may 2003 multiple protocol contactless reader ic cl rc632 92 confidential 9.4 register overview timer unit the following table shows the related flags of the timer unit in alphabetic order. flags register address tautorestart timerclock 0x2a, bit 5 timervalue timervalue 0x0c, bits 7-0 timerreloadvalue timerreload 0x2c, bits 7-0 tprescaler timerclock 0x2a, bits 4-0 trunning secondarystatus 0x05, bit 7 tstartnow control 0x09, bit 1 tstarttxbegin timercontrol 0x2b, bit 0 tstarttxend timercontrol 0x2b, bit 1 tstopnow control 0x09, bit 2 tstoprxbegin timercontrol 0x2b, bit 2 tstoprxend timercontrol 0x2b, bit 3 table 9-1 registers associated with the timer unit
philips semiconductors product s pecification rev. 3.0; may 2003 multiple protocol contactless reader ic cl rc632 93 confidential 10 power reduction modes 10.1 hard power down a hard power down is enabled with high on pin rstpd. this turns off all intern al current sinks including the oscillator. all digital input buffers are separat ed from the input pads and defined internally (except pin rstpd itself). the output pins ar e frozen at a certain value. this is shown in the following table. symbol pin type description oscin 1 i not separated from input, pulled to avss irq 2 o high impedance mfin 3 i separated from input mfout 4 o low high, if tx1rfen=1 tx1 5 o low, if tx1rfen=0 high, only if tx2rfen=1 and tx2inv=0 tx2 7 o low nwr 9 i separated from input nrd 10 i separated from input ncs 11 i separated from input d0 to d7 13 to 20 i/o separated from input ale 21 i separated from input a0 22 i/o separated from input a1 23 i separated from input a2 24 i separated from input aux 27 o high impedance rx 29 i not changed vmid 30 a pulled to avdd rstpd 31 i not changed oscout 32 o high table 10-1: signal on pins during hard power down 10.2 soft power down the soft power down-mode is entered immediately by setting bit powerdown in the control-register . all internal current sinks are switched off (including the oscillator buffer). in difference to the hard power down-mode, the digita l input-buffers are not separated by the input pads and keep their functionality. the digital output pins do not change their state. after resetting bit powerdown in the control-register it needs 512 clocks until the soft power down mode is left indicated by the powerdown bit itself. resetting it does not immediately clear it. it is cleared automatically by the cl rc632 when the soft power down-mode is left. note: if the internal oscillator is used, you have to take into account that it is supplied by avdd and it will take a certain time t osc until the oscillator is stable and the clock cycl es can be detected by the internal logic.
philips semiconductors product s pecification rev. 3.0; may 2003 multiple protocol contactless reader ic cl rc632 94 confidential 10.3 stand by mode the stand by-mode is entered immediately by setting bit standby in the control-register . all internal current sinks are switched off (including the internal digi tal clock buffer but except the oscillator buffer). different from the hard power down-mode, the digital input-buffers are not separated by the input pads and keep their functionality. the digital output pins do not change their state. different from the soft power down-mode, the oscillator does not need time to wake up. after resetting bit standby in the control-register it needs 4 clocks on pin os cin until the stand by-mode is left indicated by the standby bit itself. resetting it does not immediately clear it. it is cleared automatically by the cl rc632 when the stand by-mode is left. 10.4 receiver power down it is power saving to switch off the receiver circuit when it is not needed and switched it on again right before data is to be received from the card. this is done automatically by setting bit rxautopd to 1. if it is set to 0 the receiver is continuously switched on.
philips semiconductors product s pecification rev. 3.0; may 2003 multiple protocol contactless reader ic cl rc632 95 confidential 11 start up phase the phases executed during the start up are shown in the following figure. 11.1 hard power down phase the hard power down phase is active during the following cases: ? power on reset caused by power up at pin dvdd (active while dvdd is below the digital reset threshold) ? power on reset caused by power up at pin avdd (active while avdd is below the analog reset threshold) ? a high level on pin rstpd (active while pin rstpd is high) 11.2 reset phase the reset phase follows the hard power down phase autom atically. one?s the oscillator is running stable, it takes 512 clocks. during the reset phase, some of the r egister bits are pre-set by hardware. the respective reset values are given in the descri ption of each register (see 5.2.). note: if the internal oscillator is used, you have to take in to account that it is supplied by avdd and that it will take a certain time t osc until the oscillator is stable. 11.3 initialising phase the initialising phase follows the reset phase automa tically. it takes 128 clocks. during the initialising phase the content of the e2prom blocks 1 and 2 is copied into the registers 10 hex to 2f hex . (see 6.3) note: at production test, the cl rc632 is initialised wi th default configuration values. this reduces the -processors effort for configuring the device to a minimum. hard power down phase reset phase initialising phase ready start up phase t pd t reset t init states figure 11-1: start up procedure
philips semiconductors product s pecification rev. 3.0; may 2003 multiple protocol contactless reader ic cl rc632 96 confidential 11.4 initialising the pa rallel interface-type for the different connections for the different -proc essor interface types (see 4.3), a certain initialising sequence shall be applied to enable a proper -processo r interface type detection and to synchronise the -processor?s and the cl rc632?s start up. during the whole start up phase, the command value reads as 3f hex . at the end of the initialising phase the cl rc632 enters the idle command automatically. consequently the command value changes to 00 hex . to ensure proper detection of the -processor inte rface, the following seque nce shall be executed: ? read from the command-register until the 6 bit register value for command is 00 hex . the internal initialisation phase is now complet ed and the cl rc632 is ready to be controlled. ? write the value 80 hex to the page-register to initialise the -pr ocessor interface. ? read the command-register . if its value is 00 hex the -processor interf ace initialisation was successful. having done the interface initialisation, the linear addre ssing mode can be activated by writing 0x00 to the page register(s).
philips semiconductors product s pecification rev. 3.0; may 2003 multiple protocol contactless reader ic cl rc632 97 confidential 12 oscillator circuitry the clock applied to the cl rc632 acts as time basi s for the coder and decoder of the synchronous system. therefore stability of the cl ock frequency is an important factor for pr oper performance. to obtain highest performance, clock jitter has to be as small as possible . this is best achieved by using the internal oscillator buffer with the recommended circuitry. if an external cl ock source is used, the clock signal has to be applied to pin oscin. in this case special care for clock duty cycle and clock jitter is needed and the clock quality has to be verified. it needs to be in accordance with the specifications in chapter 22.5.3. remark: we do not recommend to use an external clock source. 15 pf 15 pf 13.56 mhz oscout oscin mf rc531 figure 12-1: quartz connection
philips semiconductors product s pecification rev. 3.0; may 2003 multiple protocol contactless reader ic cl rc632 98 confidential 13 transmitter pins tx1 and tx2 the signal delivered on tx1 and tx2 is the 13.56 mhz energy carrier modulated by an envelope signal. it can be used to drive an antenna directly, using a fe w passive components for matching and filtering (see chapter 20). for that, the output circuitry is designed with a very low impedance source resistance. the signal of tx1 and tx2 can be controlled via the txcontrol register . 13.1 configuration of tx1 and tx2 the configuration possibilities of tx 1 are described in the table below: register configuration in txcontrol tx1rfen force100ask envelope signal on tx1 0 x x low (gnd) 0 13.56 mhz carrier frequency modulated 1 0 1 13.56 mhz carrier frequency 0 low 1 1 1 13.56 mhz energy carrier table 13-1: configurations of pin tx1 the configuration possibilities of tx 2 are described in the table below: register configuration in txcontrol tx2rfen force100 ask tx2cw invtx2 envelope signal on tx2 0 x x x x low 0 13.56 mhz carrier frequency modulated 0 1 13.56 mhz carrier frequency 0 13.56 mhz carrier frequency modulated, 180 phase shift relative to tx1 0 1 1 13.56 mhz carrier frequency, 180 phase shift relative to tx1 0 x 13.56 mhz carrier frequency 0 1 1 x 13.56 mhz carrier frequency, 180 phase shift relative to tx1 0 low 0 1 13.56 mhz carrier frequency 0 high 0 1 1 13.56 mhz carrier frequency, 180 phase shift relative to tx1 0 x 13.56 mhz carrier frequency 1 1 1 1 x 13.56 mhz carrier frequency, 180 phase shift relative to tx1 table 13-2: configurations of pin tx2
philips semiconductors product s pecification rev. 3.0; may 2003 multiple protocol contactless reader ic cl rc632 99 confidential 13.2 operating distance versus power consumption the user has the possibility to find a trade-off betwe en maximum achievable operating distance and power consumption using different antenna matching circuits by varying the supply vo ltage at the antenna driver supply pin tvdd. different antenna matching circ uits are described in the application note, mifare ? design of mf rc500 matching circuit and antennas . 13.3 antenna driver output source resistance the output source conductance of tx1 and tx2 for dr iving a high level may be adjusted via the value gscfgcw in the cwconductance register in the range from about 1 up to 100 ohm. the output source conductance of tx1 and tx2 during the modul ation phase may be adjusted via the value gscfgmod in the modconductance register in the same range . the values given are relative to the reference resistance rs rel , that is measured during production test and stored in the cl rc632 e2prom. it can be obtained from the product information field (see chapter 6.2). the electr ical specification can be found in chapter 22.4.3.
philips semiconductors product s pecification rev. 3.0; may 2003 multiple protocol contactless reader ic cl rc632 100 confidential 13.3.1 source resistance table gscfgcw, gscfgmod [decimal] exp gscfgcw, exp gscfgmod [decimal] mant gscfgcw, mant gscfgmod [decimal] rs rel [ohm] gscfgcw, gscfgmod [decimal] exp gscfgcw, exp gscfgmod [decimal] mant gscfgcw mant gscfgmod [decimal] rs rel [ohm] 0 0 0 24 1 8 0,0652 16 1 0 25 1 9 0,0580 32 2 0 37 2 5 0,0541 48 3 0 26 1 10 0,0522 1 0 1 1,0000 27 1 11 0,0474 17 1 1 0,5217 51 3 3 0,0467 2 0 2 0,5000 38 2 6 0,0450 3 0 3 0,3333 28 1 12 0,0435 33 2 1 0,2703 29 1 13 0,0401 18 1 2 0,2609 39 2 7 0,0386 4 0 4 0,2500 30 1 14 0,0373 5 0 5 0,2000 52 3 4 0,0350 19 1 3 0,1739 31 1 15 0,0348 6 0 6 0,1667 40 2 8 0,0338 7 0 7 0,1429 41 2 9 0,0300 49 3 1 0,1402 53 3 5 0,0280 34 2 2 0,1351 42 2 10 0,0270 20 1 4 0,1304 43 2 11 0,0246 8 0 8 0,1250 54 3 6 0,0234 9 0 9 0,1111 44 2 12 0,0225 21 1 5 0,1043 45 2 13 0,0208 10 0 10 0,1000 55 3 7 0,0200 11 0 11 0,0909 46 2 14 0,0193 35 2 3 0,0901 47 2 15 0,0180 22 1 6 0,0870 56 3 8 0,0175 12 0 12 0,0833 57 3 9 0,0156 13 0 13 0,0769 58 3 10 0,0140 23 1 7 0,0745 59 3 11 0,0127 14 0 14 0,0714 60 3 12 0,0117 50 3 2 0,0701 61 3 13 0,0108 36 2 4 0,0676 62 3 14 0,0100 15 0 15 0,0667 63 3 15 0,0093 table 13-3: source resistance of n-channel driver transistor of tx1 and tx2 vs. gsconfcw or gscfgmod
philips semiconductors product s pecification rev. 3.0; may 2003 multiple protocol contactless reader ic cl rc632 101 confidential 13.3.2 formula for the source resistance the relative resistance rs rel can be calculated by gscfgcw exp gscfgcw rel mant rs ) ( 1 40 77 ? = the relative resistance rs rel during the modulation phase can be calculated using gscfgmod , respectively. 13.3.3 calculating the effe ctive source resistance 13.3.3.1 wiring resistance wiring and bonding add a constant offset to the driver resistance, that is relevant if tx1 and tx2 are switched to low impedance. the additional resistance for tx1 can be set approximately to ? m rs tx wire 500 1 , 13.3.3.2 effective resistance the source resistances of the driver transistors r smaxp found in the product information field (see chapter 6.2) are measured at production test with gscfgcw set to 01 hex . to get the driver resistance for a specific value set in gscfgmod the following formula may be used: ( ) 1 , 1 , max, , tx wire rel tx wire p ref x rs rs rs rs rs + ? ? = .
philips semiconductors product s pecification rev. 3.0; may 2003 multiple protocol contactless reader ic cl rc632 102 confidential 13.4 pulse width the envelope carries the information of the data signal that shall be transmitted to the card done by coding the data signal according to the miller code. furtherm ore, each pause of the miller coded signal again is coded as a pulse of certain length. the width of this pulse can be adjusted by means of the modwidth register . the pulse length is calculated by c pulse f modwidth t 1 2 + = where f c = 13.56mhz.
philips semiconductors product s pecification rev. 3.0; may 2003 multiple protocol contactless reader ic cl rc632 103 confidential 14 receiver circuitry 14.1 general the cl rc632 employs an integrated quadrature-demodul ation circuit giving the possibility to detect an iso 14443 compliant subcarrier signal applied to pin rx. the iso14443-a sub-carrier signal is defined as a manchester coded ask-modulated signa l. the iso14443-b sub- carrier signal is defined as an nrz-l coded bpsk modulated iso14443-b s ub-carrier signal. the quadrature-demodulator uses two different clocks, q- and i -clock, with a phase shift of 90 between them. both resulting sub-carrier signals are amplified, filtered and forwarded to a correlation circuitry. the correlation results are evaluated, digitis ed and passed to the digital circuitry. for all processing units various adjustments can be made to obtain optimum performance. 14.2 block diagram figure 14-1 shows the block di agram of the receiver circuitry. the re ceiving process includes several steps. first the quadrature demodulation of the carrier sig nal of 13.56 mhz is done. to achieve an optimum in performance an automatic clock q calibration is reco mmended (see 14.3.1). the demodulated signal is amplified by an adjustable amplifier. a correlation ci rcuit calculates the degree of similarity between the expected and the received signal. the bit phase regist er allows aligning the position of the correlation intervals with the bit grid of the received signal. in the evaluation and digitizer circuitry the valid bits are detected and the digital results are send to the fifo regi ster. several tuning steps in this circuit are possible. the user may observe the signal on its way through t he receiver as shown in the block diagram above. one signal at a time may be routed to pin aux using the testanaselect-register as described in 21.3. 13.56 mhz demodulator rx i to q conversion q-clock i-clock correlation circuitry vrxfoll i vrxfollq vrxamp i vrxampq vcorrn i vcorrdq vcorrd i vcorrnq vevall vevalr to testana outsel gain[1:0] evaluation and digitizer circuitry s_valid s_data s_coll s_clock bitphase[7:0] minlevel[3:0] colllevel[3:0] clockqcalib clockqdelay[4:0] clockq180 clock rcvclksel i rxwait[7:0] figure 14-1: block diagram of receiver circuitry
philips semiconductors product s pecification rev. 3.0; may 2003 multiple protocol contactless reader ic cl rc632 104 confidential 14.3 putting the receiver into operation in general, the default settings programmed in the start up initialisation file are suitable to use the cl rc632 for data communication with mifare ? cards. however, in some environments specific user settings may achieve better performance. 14.3.1 automatic cl ock-q calibration the quadrature demodulation concept of the receiver generates a phase si gnal i-clock and a 90-shifted quadrature signal q-clock. to achieve an optim um demodulator performance, the q- and the i -clock have to have a difference in phase of 90. after the reset phase of the cl rc632, a calibration procedure is done automatically. it is possible to have an automatic calibration done at the ending of each transceive command. to do so, the clkqcalib bit has to be configured to a value of 0. configuring this bit to a constant value of 1 disables all automatic calibrations except the one after the reset sequence. it is also possible to initiate one automatic calibration by software. this is done with a 0 to 1 transition of bit clkqcalib. the details: note : the duration of the automatic cloc k q calibration takes 65 oscillator periods which is approx. 4,8s. the value of clkqdelay is proportional to the phase shift between the q- and the i -clock. the status flag clkq180deg shows, that the phase shift between the q- and the i -clock is greater than 180. notes: ? the start-up configuration file enables an autom atically q-clock calibration after the reset. ? while clkqcalib is 1, no automatic calibration is done. therefore leaving this bit 1 can be used to permanently disable the automatic calibration. ? it is possible to write data to clkqdelay via the -processor. the aim could be a disabling of the automatic calibration and to pre-set the delay by softw are. but notice, that configuring the delay value by software requires that bit clkqcalib has already been set to 1 before and that a time interval of at least 4.8s has elapsed since then. each delay value must be written with the clkqcalib bit set to 1. if clkqcalib is 0 the configured delay value will be overwritten by the next in terval automatic calibration. calibration impulse from reset sequence a rising edge initiates a clock q calibration calibration impulse from ending of transeive command the clkqcalib bit
philips semiconductors product s pecification rev. 3.0; may 2003 multiple protocol contactless reader ic cl rc632 105 confidential 14.3.2 amplifier the demodulated signal has to be amplified with the vari able amplifier to achieve the best performance. the gain of the amplifiers can be adjusted by means of the register bits gain [1:0] . the following gain factors are selectable: register setting gain factor [db] (simulation results) 0 20 1 24 2 31 3 35 table 14-1: gain factors for the internal amplifier
philips semiconductors product s pecification rev. 3.0; may 2003 multiple protocol contactless reader ic cl rc632 106 confidential 14.3.3 correlation circuitry the correlation circuitry calculates the degree of matching between the received and an expected signal. the output is a measure for the amplit ude of the expected signal in the re ceived signal. this is done for both, the q- and the i -channel. the correlator delivers two outputs for ea ch of the two input channels, resulting in four output signals in total. for optimum performance, the correlation circuitry needs the phase information for the signal coming from the card. this information has to be defined by the -processor by m eans of the register bitphase [7:0] . this value defines the phase relation between the tran smitter and receiver clock in multiples of t bitphase = 1/13.56 mhz. 14.3.4 evaluation and digitizer circuitry for each bit-half of the manchester coded signal t he correlation results are ev aluated. the evaluation and digitizer circuit decides from the signal strengths of both bit-halves, whether the current bit is valid, and, if it is valid, the value of the bit itself or whether the current bit-interval contains a collision. to do this in an optimum way, the user may select the following levels: ? minlevel : defines the minimum signal strength of the str onger bit-half?s signal for being considered valid. ? colllevel : defines the minimum signal strength that ha s to be exceeded by the weaker half-bit of the manchester-coded signal to generate a bit-collision. if the signal?s strength is below this value, a 1 and 0 can be determined unequivocally. colllevel defines the minimum signal strength relati ve to the amplitude of the stronger half-bit. after transmission of data, the card is not allowed to send its response before a ce rtain time period, called frame guard time in the standard iso14443. the length of this time period after transmission shall be set in the rxwait-register . the rxwait-register defines when the receiver is switched on after data transmission to the card in multiples of one bit-duration. if register bit rcvclksel i is set to 1, the i -clock is used to clock the correlat or and evaluation circuits. if set to 0, the q-clock is used. note : it is recommended to use the q-clock.
philips semiconductors product s pecification rev. 3.0; may 2003 multiple protocol contactless reader ic cl rc632 107 confidential 15 serial signal switch 15.1 general two main blocks are implemented in the cl rc632. a digital circuitry, comprising state machines, coder and decoder logic and so on and an analog circuitry with the modulator and antenna drivers, receiver and amplification circuitry. the interface between thes e two blocks can be configur ed in the way, that the interfacing signals may be routed to the pins mfin and mfout. this topology supports, that the analog part of the one cl rc632 may be connected to the digital part of another device. the serial signal switch can be used to measure mifare? and iso14443 as well i ? code1 and iso15693 related signals. note: the mfin pin can only be accessed by 106 kbaud according to iso14443a . the manchester with subcarrier- and the manchester signal can only be accessed at the mfout pin at 106 kbaud according to iso14443a. 15.2 block diagram figure 15-1 describes the serial signal switches. three di fferent switches are implemented in the serial signal switch in order to use the cl rc632 in different configurations. the serial signal switch may also be used during the design in phase or for test purposes to check the transmitted and received data. chapter 21.2 describes analog test signals as well as measurements at the serial signal switch. note: the sl rc400 uses the name sigout for the mfout pin. the clrc 632 functionality includes the (part of) analog circuitry rx tx1 tx2 manchester decoder miller coder 1 out of 256, rz or 1 out of 4 modulator driver 0 1 2 3 2 modulator source 0 1 envelope mfin mfout mfout select 3 0 1 2 3 4 5 6 7 0 1 envelope transmitt nrz rfu manchester rfu manchester with subcarrier 0 1 2 3 2 decoder source 0 internal manchester with subcarrier manchester serial data out serial data in mfin subcarrier demodulator carrier demodulator subcarrier demodulator serial signal switch (part of) serial data processing manchester out 0 1 signalto mfout digital test signal figure 15-1: serial signal switch
philips semiconductors product s pecification rev. 3.0; may 2003 multiple protocol contactless reader ic cl rc632 108 confidential test possibilities for the sl rc 400 using the pin mfout. the following chapters describe the relevant registers us ed to configure and control the serial signal switch. 15.3 registers relevant for the serial signal switch the flags decodersource define the input signal for the internal manchester decoder in the following way: decodersource input signal for decoder 0 constant 0 1 output of the analog part. this is the default configuration. 2 direct connection to mfin, expecting an 847.5 khz sub-carrier signal modulated by a manchester coded signal. 3 direct connection to mfin, expecting a manchester coded signal. table 15-1: values for decodersource modulatorsource defines the signal that modulates the trans mitted 13.56 mhz energy carrier. the modulated signal drives the pins tx1 and tx2. modulatorsource input signal for modulator 0 constant 0 (energy carrier off at pin tx1 and tx2). 1 constant 1 (continuous energy carrier delivered at pin tx1 and tx2). 2 modulation signal (envelope) from the internal coder. this is the default configuration. 3 direct connection to mfin, expecting a miller pulse coded signal. table 15-2: values for modulatorsource mfoutselect selects the output signal, whic h is routed to the pin mfout. mfoutselect signal routed to pin mfout 0 constant low 1 constant high 2 modulation signal (envelope) from the internal coder. 3 serial data stream that is to be transmitted (same as for mfoutselect = 2, but not coded by the selected pulse coder yet). 4 output signal of the receiver circuit (card modulation signal regenerated and delayed) 5 output signal of the subcarrier dem odulator (manchester-coded card signal) 6 rfu 7 rfu able 15-3: values for mfoutselect to use mfoutselect , the value of test signal control bit signaltomfout has to be 0.
philips semiconductors product s pecification rev. 3.0; may 2003 multiple protocol contactless reader ic cl rc632 109 confidential mifare ? : usage of the mfin and mfout 15.3.1 active antenna concept the cl rc632 analog circuitry may be used via the pins mfin and mfout. to do so, the following register settings have to be made: register value signal at cl rc632 pin modulatorsource 3 miller pulse coded mfin mfoutselect 4 manchester coded with sub-carrier mfout decodersource x - - table 15-4: register setting to us e the cl rc632 analog circuitry only on the other hand, the cl rc632 digital circuitry may be used via the pins mfin and mfout. to do so, the following register settings have to be made: register value signal at cl rc632 pin modulatorsource x - - mfoutselect 2 miller pulse coded mfout decodersource 2 manchester coded with sub-carrier mfin table 15-5: register setting to use the cl rc632 digital circuitry only two cl rc632 devices configured in the above descri bed way may be connected to each other via the pins mfout and mfin. note: the usage of the active antenna concept is only possible with a baudrate of 106kbaud according to iso14443a. 15.3.2 driving two rf-parts it is possible, to connect a ?passive antenna? to pins tx1, tx2 and rx (via the appr opriate filter and matching circuit) and at the same time an acti ve antenna to the pins mfout and mfin. in this configuration, two rf-parts may be driven (one after another) by one -processor.
philips semiconductors product s pecification rev. 3.0; may 2003 multiple protocol contactless reader ic cl rc632 110 confidential 16 mifare ? higher baudrates the mifare ? classic system is specified with a fix baud- rate of 106 kbaud for the communication on the rf interface. iso 14443 in the existing version also de fines 106 kbaud at least for the initial phase of a communication between picc and pcd. to speed up the communication between a terminal and a card to cover requirements for large data transmission the cl rc632 supports the mifare ? higher baudrates communication in combination with e.g. a controller ic like the mifare ? prox. communication direction baudrates [kbaud] cl rc632 based pcd c picc supporting higher baudrates 106, 212, 424 c picc supporting higher baudrates cl rc632 based pcd 106, 212, 424 table 16-1 mifare ? higher baudrates the mifare ? higher baudrates? concept will be de scribed in the application note: ? mifare ? implementation of higher baudrates?. this application note will cove r also the integration a mifare ? higher baudrates communication concept in current applications.
philips semiconductors product s pecification rev. 3.0; may 2003 multiple protocol contactless reader ic cl rc632 111 confidential 17 iso14443 b the international standard iso14443 standard cove rs 2 communication schemes: the iso14443-a and the iso14443-b. the cl rc632 reader ic fully supports the iso14443. the following registers and flags cover the iso 14443b communication scheme: flags register address charspacing typebframing 0x17, bits 4-3 coderrate codercontrol 0x14, bits 5-3 eofwidth typebframing 0x17, bit 5 filterampdet bpskdemcontrol 0x1d, bit 4 force100ask txcontrol 0x11, bit 4 gscfgcw cwconductance 0x12, bits 5-0 gscfgmod modconductance 0x13, bits 5-0 minlevel rxtreshhold 0x1c, bits 7-4 notxeof typebframing 0x17, bit 6 notxsof typebframing 0x17, bit 7 norxegt bpskdemcontrol 0x1d, bit 6 norxeof bpskdemcontrol 0x1d, bit 5 norxsof bpskdemcontrol 0x1d, bit 7 rxcoding decodercontrol 0x1a,bit 0 rxframing decodercontrol 0x1a,bits 4-3 sofwidth typebframing 0x17,bits 1-0 subcpulses rxcontrol1 0x19, bits 7-5 taub bpskdemcontrol 0x1d, bits 1-0 taud bpskdemcontrol 0x1d, bits 3-2 txcoding codercontrol 0x14, bits 2-0 table 17-1 registers associated with iso14443-b as a reference documentation the international standard iso14443 ?identification cards- contactless integrated circuit(s) cards- proximity cards, part 1-4? can be taken. note: philips semiconductors does not offer a basic function library to design in the iso14443 b protocol.
philips semiconductors product s pecification rev. 3.0; may 2003 multiple protocol contactless reader ic cl rc632 112 confidential 18 cl rc632 command set 18.1 general description the cl rc632 behaviour is determined by an internal state machine capable to perform a certain set of commands. the commands can be started by writing the according command-code to the command- register . arguments and/or data necessary to process a co mmand are mainly exchanged via the fifo buffer. 18.2 general behaviour ? each command, that needs a data stream (or data by te stream) as input will immediately process the data it finds in the fifo buffer. ? each command that needs a certain number of argument s will start processing only when it has received the correct number of arguments via the fifo buffer. ? the fifo buffer is not cleared automatically at command start. therefore, it is also possible to write the command arguments and/or the data bytes into t he fifo buffer and start the command afterwards. ? each command (except the startup-command ) may be interrupted by the -processor by writing a new command code into the command-register e.g.: the idle-command . 18.3 cl rc632 commands overview command code action arguments and data passed via fifo returned data via fifo see chapter startup 3f hex runs the reset- and initialisation phase. note: this command can not be activated by software, but only by a power-on or hard reset - - 18.3.2 idle 00 hex no action; cancels current command execution. - - 18.3.3 transmit 1a hex transmits data from the fifo buffer to the card. data stream - 18.4.1 receive 16 hex activates receiver circuitry. note: before the receiver actually starts, the state ma chine waits until the time configured in the register rxwait has passed. note: this command may be used for test purposes only, since there is no timing relation to the transmit- command . - data stream 18.4.2
philips semiconductors product s pecification rev. 3.0; may 2003 multiple protocol contactless reader ic cl rc632 113 confidential cl rc632 commands overview continued command code action arguments and data passed via fifo returned data via fifo see chapter transceive 1e hex transmits data from fifo buffer to the card and activates automatically the receiver after transmission. note: before the receiver actually starts, the cl rc632 waits until the time configured in the register rxwait has passed. note: this command is the combination of transmit and receive data stream data stream 18.4.3 writee2 01 hex gets data from fifo buffer and writes it to the internal e2prom. start address lsb start address msb data byte stream - 18.6.1 reade2 03 hex reads data from the internal e2prom and puts it into the fifo buffer. note: keys cannot be read back start address lsb start address msb number of data bytes data bytes 18.6.2 loadkeye2 0b hex copies a key from the e2prom into the key buffer. note : related to mifare? classic security start address lsb start address msb - 18.9.1 loadkey 19 hex reads a key from the fifo buffer and puts it into the key buffer. note: the key has to be prepared in a specific format (refer to 6.4.1, key format) note : related to mifare? classic security byte0 (lsb) byte1 ? byte 10 byte11 (msb) - 18.9.2 authent1 0c hex performs the first part of the crypto1 card authentication. note : related to mifare? classic security card?s auth-command card?s block address card?s serial number lsb card?s serial number byte1 card?s serial number byte2 card?s serial number msb - 18.9.3 authent2 14 hex performs the second part of the card authentication us ing the crypto1 algorithm. note : related to mifare? classic security - - 18.9.4 loadconfig 07 hex reads data from e2prom and initialises the cl rc632 registers. start address lsb start address msb - 18.7.1 calccrc 12 hex activates the crc-coprocessor. note: the result of the crc calculation can be read from the registers crcresultlsb and crcresultmsb data byte-stream - 18.7.2 table 18-1: cl rc632 command overview
philips semiconductors product s pecification rev. 3.0; may 2003 multiple protocol contactless reader ic cl rc632 114 confidential 18.3.1 basic states 18.3.2 startup command 3f hex command code hex action arguments and data returned data startup 3f runs the reset- and initialisation phase note: this command can not be activated by software, but only by a power-on or hard reset - - the startup-command runs the reset- and initialisation phase. it does not need or return any data. it can not be activated by the -processo r but is started automatically a fter one of the following events: ? power on reset caused by power up at pin dvdd ? power on reset caused by power up at pin avdd ? negative edge at pin rstpd the reset-phase defines certain register bits by an asynchronous reset. the initialisation-phase defines certain registers with values taken from the e2prom. when the startup-command has finished, the idle-command is entered automatically. notes: ? the -processor must not write to the cl rc632 as long as the cl rc632 is busy executing the startup-command . to ensure this, the -processor shall poll for the idle-command to determine the end of the initialisation phase (see also chapter 11.4). ? as long as the startup-command is active, only reading from page 0 of the cl rc632 is possible. ? the startup-command can not be interrupted by the -processor. 18.3.3 idle command 00 hex command code hex action arguments and data returned data idle 00 no action, cancels current command execution - - the idle-command switches the cl rc632 to its inactive stat e. in this idle-state it waits for the next command. it does not need or return any data. the dev ice automatically enters the idle-state when a command finishes. in this case the cl rc632 simultaneously initiates an interrupt request by setting bit idleirq . triggered by the -processor, the idle-command may be used to stop execution of all other commands (except the startup command ). in that case no idleirq is generated. remark: stopping a command with the idle command does not clear the fifo buffer content.
philips semiconductors product s pecification rev. 3.0; may 2003 multiple protocol contactless reader ic cl rc632 115 confidential 18.4 commands for iso14443 a card communication the cl rc632 is a fully iso 14443 and iso15693 and i ? code1 compliant reader ic. therefore, the command set of this ic allows more flexibility and more generalised commands compared to mifare ? or i ? code1 dedicated reader ics. the following chapter describes the command set for card communication for iso14443 a related communication schemes. 18.4.1 transmit command 1a hex command code hex action arguments and data returned data transmit 1a transmits data from fifo buffer to the card data stream - the transmit-command takes data from the fifo buffer and forwards it to the transmitter. it does not return any data. the transmit-command can only be started by the -processor. 18.4.1.1 working with the transmit command to transmit data one of the following sequences may be used: 1. all data, that shall be transmitted to the card is written to the fifo while the idle-command is active. after that, the command code for the transmit-command is written to the command-register . note: this is possible for transmission of data with a length of up to 64 bytes. 2. the command code for the transmit-command is written to the command-register first. since no data is available in the fifo, the command is only enabled but transmission is not triggered yet. data transmission really starts with the first data by te written to the fifo. to generate a continuous data stream on the rf-interface, the -processor has to put the next data bytes to the fifo in time. note: this allows transmission of data of any length but requires that data is available in the fifo in time. 3. a part of the data, that shall be transmitted to the card is written to the fifo while the idle-command is active. after that, the command code for the transmit-command is written to the command-register . while the transmit-command is active, the -processor may feed fu rther data to the fifo, causing the transmitter to append it to the transmitted data stream. note: this enables transmission of data of any length but requires that data is available in the fifo in time. when the transmitter requests the next data byte to keep the data stream on the rf-interface continuous but the fifo buffer is empty, the transmit-command automatically terminates. this causes the internal state machine to change its state from transmit to idle. if data transmission to the card is finished, the cl rc632 sets the flag txirq to signal it to the -processor. remark: if the -processor overwrites the transmit code in the command-register with the idle-command or any other command, transmission stops immediately with the next clock cycle. this may produce output signals that are not according to iso14443-a. 18.4.1.2 rf-channel redundancy and framing each transmitted iso14443 frame consists of a sof (s tart of frame) pattern, followed by the data stream and is closed by an eof (end of frame) pattern. these different phases of the transmit sequence may be monitored by watching modemstat e of primarystatus-register (see 18.4.4).
philips semiconductors product s pecification rev. 3.0; may 2003 multiple protocol contactless reader ic cl rc632 116 confidential depending on the setting of bit txcrcen in the channelredundancy-register a crc is calculated and appended to the data stream. the crc is calculated according the settings in the channelredundancy register . parity generation is handled according the settings in the channelredundancy-register (bits parityen and parityodd) . 18.4.1.3 transmission of bit oriented frames the transmitter may be configured to send an incomplete last byte. to achieve this txlastbits has to be set to a value unequal zero. this is shown in the figure below. the figure shows the data stream if parityen is set in channelredundancy-register . all fully transmitted bytes are followed by a parity check bit, but the in complete byte is not followed by a parity check bit. after transmission, txlastbits is cleared automatically. note: if txlastbits is not equal to zero crc generation has to be disabled. this is done by clearing the bit txcrcen in the channelredundancy register . bit7 bit0 sof p bit7 bit0 p eof bit7 bit0 sof pbit6 bit0 eof bit7 bit0 sof pbit0 eof txlastbits = 0 txlastbits = 7 txlastbits = 1 figure 18-1: transmitting bit oriented frames
philips semiconductors product s pecification rev. 3.0; may 2003 multiple protocol contactless reader ic cl rc632 117 confidential 18.4.1.4 transmission of frames with more than 64 bytes to generate frames with more than 64 bytes, the -proc essor has to write data into the fifo buffer while the transmit command is active. the state machine checks the fifo status when it starts transmitting the last bit of the actual data stream (the check time is marked below with arrows). as long as the internal signal ?accept further data ? is 1 further data may be loaded to the fifo. the cl rc632 appends this data to the data str eam transmitted via the rf-interface. if the internal signal ?accept further data? is 0 the tran smission will terminate. all data written into the fifo buffer after ?accept further data? went 0 will not be tr ansmitted anymore, but remain in the fifo buffer. remark: if parity generation is enabled ( parityen bit is 1) the parity bit is the last bit to be transmitted. this delays the signal ?accept further data? for one bit duration. fifo length fifo empty 0x01 0x00 txlastbits = 0 txlastbits bit0 bit7 bit0 bit7 txdata check fifo empty accept further data bit7 figure 18-2: timing for transmi tting byte oriented frames
philips semiconductors product s pecification rev. 3.0; may 2003 multiple protocol contactless reader ic cl rc632 118 confidential if txlastbits is unequal zero the last byte is not transmitt ed completely, but only the number of bits set in txlastbits are transmitted (starting with the least significant bit). thus, the internal state machine has to check the fifo st atus at an earlier point in time (shown in the figure below). since txlastbits = 4 in this example, transmission stops after bi t 3 is transmitted. if configured, the frame is completed with an eof. the figure above also shows a write access to the fifodata register right before the fifo?s status is checked. this leads to ?fifo empty? going to 0 agai n and therefore ?accept further data? stays active. the new byte written is transmitted via the rf-interface. ?accept further data? is changed only by the ?check fifo empty? function. this function verifies ?fifo empty? one bit duration before the last expected bit transmission. frame definition verification at: 8 bit with parity 8 th bit 8 bit without parity 7 th bit x bit without parity (x-1) th bit fifo length fifo empty 0x01 0x00 txlastbits = 4 txlastbits bit0 bit7 bit0 txdata check fifo empty accept further data bit7 bit3 bit4 n_wr (fifo data) 0x00 0x01 bit3 bit4 figure 18-3: timing for transmitting bit oriented frames
philips semiconductors product s pecification rev. 3.0; may 2003 multiple protocol contactless reader ic cl rc632 119 confidential 18.4.2 receive command 16 hex command code hex action arguments and data returned data receive 16 activates receiver circuitry - data stream the receive-command activates the receiver circuitry. all data re ceived from the rf interface is returned via the fifo buffer. the receive-command can be started either by the - processor or automatically during execution of the transceive-command . note: this command may be used for test purposes only, since there is no timing relation to the transmit- command . 18.4.2.1 working with the receive command after starting the receive command the internal state machine decrements the value set in the rxwait- register with every bit-clock. from 3 down to 1 the anal og receiver circuitry is prepared and activated. when the counter reaches 0, the receiver starts monitoring the incoming signal at the rf-interface. if the signal strength reaches a level higher than the value set in the minlevel-register it finally starts decoding. the decoder stops, if no more signal can be detected on the receiver input pin rx. the decoder indicates termination of operation by setting bit rxirq . the different phases of the receive sequence may be monitored by watching modemstate of the primarystatus-register (see 18.4.4). note: since the counter values from 3 to 0 are necess ary to initialise the analog receiver circuitry the minimum value for rxwait is 3. 18.4.2.2 rf-channel redundancy and framing the decoder expects a sof pattern at the beginning of each data stream. if a sof is detected, it activates the serial to parallel converter and gathers the incoming data bits. every completed byte is forwarded to the fifo. if an eof pattern is detected or the signal strength falls below minlevel set in the rxthreshold register , the receiver and the decoder stop, the idle-command is entered and an appropriate response for the -processor is generated (interrupt request activated, status flags set). if bit rxcrcen in the channelredundancy register is set a crc block is expected. the crc block may be one byte or two bytes according to bit crc8 in the channelredundancy register . remark: the received crc block is not forwarded to the fi fo buffer if it is corr ect. this is realised by shifting the incoming data bytes through an internal buffer of either one or two bytes (depending on the defined crc). the crc block remains in this internal buffer. as a consequence all data bytes are available in the fifo buffer one or two bytes delayed. if the crc fails all received bytes are forwarded to the fifo buffer (including the faulty crc itself). if parityen is set in the channelredundancy register a parity bit is expected after each byte. if bit parityodd is set to 1, the expected parity is an odd parity, otherwise an ev en parity is expected.
philips semiconductors product s pecification rev. 3.0; may 2003 multiple protocol contactless reader ic cl rc632 120 confidential 18.4.2.3 collision detection if more than one card is within the rf-field during the card selection phase, they will respond simultaneously. the cl rc632 supports the algorithm defined in iso 14443-a to resolve data-collisions of cards serial numbers by doing the so-called anti- collision procedure. the basis for this is the ability to detect bit- collisions. bit-collision detection is supported by the used bit- coding scheme, namely the manchester-coding. if in the first and second half-bit of a bit a sub-carrier modulati on is detected, instead of forwarding a 1 or a 0 a bit collision will be signalled. to distinguish a 1 or 0-bit from a bit-collision, the cl rc632 uses the setting of colllevel . if the amplitude of the half-bit with smaller amplitude is larger than defined by colllevel , the cl rc632 indicates a bit-collision. if a bit-collision is detec ted, the error flag collerr is set. if a bit-collision is detected in a parity bit, the flag parityerr is set indicating a parity error. independent from the detected collision the receiver continues receiving t he incoming data stream. in case of a bit-collision, the decoder forwar ds 1 at the collision position. note: as an exception, if bit zeroaftercoll is set, all bits received after the first bit-collision are forced to zero, regardless whether a bit-collision or an unequivocal st ate has been detected. th is feature eases for the software to carry out the anti-collisi on procedure defined in iso14443-a. when the first bit collision in a frame is detected, the bit position of this collision is stored in the collpos register . the collision position follows the table below: collision in bit value of collpos sof 0 lsbit of lsbyte 1 ? ? msbit of lsbyte 8 lsbit of second byte 9 ? ? msbit of second byte 16 lsbit of third byte 17 ? ? table 18-2: returned values for bit collision positions the parity bits are not counted in collpos , since a bit-collision in a parity bit per definition succeeds a bit- collision in the data bits. if a collision is detected in the sof a frame error is reported and no data is forwarded to the fifo buffer. in this case the re ceiver continues to monitor the incoming signal and generates the correct notifications to the -processor when the ending of the faulty input stream is detected. this helps the -processor to determine the time wh en it is allowed next to send anything to the card.
philips semiconductors product s pecification rev. 3.0; may 2003 multiple protocol contactless reader ic cl rc632 121 confidential 18.4.2.4 receiving bit oriented frames the receiver can handle byte streams with incomplete by tes, resulting in bit oriented frames. to support this, the following values may be used: ? rxalign selects a bit offset for the first incoming byte, e.g. if rxalign is set to 3, the first 5 bits received are forwarded to the fifo buffer. further bits ar e packed into bytes and fo rwarded. after reception, rxalign is cleared automatically. if rxalign is set to zero, all incoming bits are packed into one byte. ? rxlastbits returns the number of bits valid in the last received byte, e.g. if rxlastbits evaluates to 5 at the end of the receiving command, the 5 least significant bits are valid. rxlastbits evaluates to zero if the last byte is complete. rxlastbits is valid only, if no frame error is indicated by the flag frameerr . if rxalign is set to a value other than zero and also parityen is active, the first parity bit is not checked but ignored. 18.4.2.5 communication errors the following table shows which event causes the setting of error flags: cause bit, that is set received data did not start with a sof pattern. framingerr the crc block is not equal the expected value. crcerr the received data is shorter than the crc block. crcerr the parity bit is not equal the expected value (e. g. a bit collision occurs when a parity is expected) parerr a collision is detected. collerr table 18-3: communication error table
philips semiconductors product s pecification rev. 3.0; may 2003 multiple protocol contactless reader ic cl rc632 122 confidential 18.4.3 transceive command 1e hex command code hex action arguments and data returned data transceive 1e transmits data from fifo buffer to the card and then activates automatically the receiver data stream data stream the transceive-command first executes the transmit-command (see 18.4.1) and then automatically starts the receive-command (see 18.4.2). all data that shall be transmi tted is forwarded via the fifo buffer and all data received is returned via the fifo buffer. the transceive-command can be started only by the -processor. note: to adjust the timing relation between transmitting and receiving, the rxwait register is used to define the time delay from the last bit transmitted until the receiver is activated. furthermore, the bitphase register determines the phase-shift between the tr ansmitter and the receiver clock. 18.4.4 states of the card communication the actual state of the transmitter and re ceiver state machine can be fetched from modemstate in the primarystatus register . the assignment of modemstate to the internal action is shown in the following table: modemstate name of state description 000 idle neither the transmitter nor the receiver is in operation, since none of them is started or the transmitter has not got input data 001 txsof transmitting the ?start of frame? pattern 010 txdata transmitting data from the fifo buffer (or redundancy check bits) 011 txeof transmitting the ?end of frame? pattern gotorx1 intermediate state pa ssed, when receiver starts 100 gotorx2 intermediate state passe d, when receiver finishes 101 preparerx waiting until the time period selected in the rxwait register has expired 110 awaitingrx receiver activated; awaiting an input signal at pin rx 111 receiving receiving data table 18-4: meaning of modemstate
philips semiconductors product s pecification rev. 3.0; may 2003 multiple protocol contactless reader ic cl rc632 123 confidential 18.4.5 state diagram for the card communication gotorx1 (100) preparerx (101) awaitingrx (110) receiving (111) idle (000) c o m m a n d = r e c e i v e next bit clock frame received gotorx2 (100) rxwaitcounter = 0 signal strength > minlevel txsof (001) txdata (010) txeof (011) f i f o n o t e m p t y a n d c o m m a n d = ( t r a n s m i t o r t r a n s c e i v e ) sof transmitted eof transmitted and command = transmit data transmitted eof transmitted and command = transceive set commandregister = idle (000) command = (transmit or receive or transceive) rxmultiple = 1 end of receive frame and rxmultiple = 0 figure 18-4: state diagram: card communication
philips semiconductors product s pecification rev. 3.0; may 2003 multiple protocol contactless reader ic cl rc632 124 confidential 18.5 commands for i ? code1 and iso15693 label communication the cl rc632 is a fully iso 14443 and iso15693 and i ? code1 compliant reader ic. therefore, the command set of this ic allows more flexibility and more generalised commands compared to mifare ? or i ? code1 dedicated reader ics. the following chapter describes the command set for card communication for i ? code1 and iso15693 related communication schemes in general. 18.5.1 transmit command 1a hex command code hex action arguments and data returned data transmit 1a transmits data from fifo buffer to the label data stream - the transmit-command takes data from the fifo buffer and forwards it to the transmitter. it does not return any data. the transmit-command can only be started by the -processor. 18.5.1.1 working with the transmit command to transmit data one of the following sequences may be used: 1. all data, that shall be transmitted to the label is written to the fifo while the idle-command is active. after that, the command code for the transmit-command is written to the command-register . note: this is possible for transmission of data with a length of up to 64 bytes. 2. the command code for the transmit-command is written to command-register first. since no data is available in the fifo, the command is only enabled but transmission is not triggered yet. data transmission really starts with the first data by te written to the fifo. to generate a continuous data stream on the rf-interface, the -processor has to put the next data bytes to the fifo in time. note: this allows transmission of data of any length but requires that data is available in the fifo in time. 3. a part of the data, that shall be transmit to the label is written to the fifo while the idle-command is active. after that, the command code for the transmit-command is written to the command-register . while the transmit-command is active, the -processor may feed fu rther data to the fifo, causing the transmitter to append it to the transmitted data stream. note: this enables transmission of data of any length but requires that data is available in the fifo in time. when the transmitter requests the next data byte to keep the data stream on the rf-interface continuous but the fifo buffer is empty, the transmit-command automatically terminates. this causes the internal state machine to change its state from transmit to idle. if data transmission to the label is finished, the cl rc632 sets the flag txirq to signal it to the -processor. remark: if the -processor overwrites the transmit code in the command-register with the idle-command or any other command, transmission stops immediately with the next clock cycle. this may produce output signals that are not according to the standard iso 15693 or the i ? code1 protocol.
philips semiconductors product s pecification rev. 3.0; may 2003 multiple protocol contactless reader ic cl rc632 125 confidential 18.5.1.2 rf-channel redundancy and framing each transmitted iso 15693 frame consists of a sof (s tart of frame) pattern, followed by the data stream and is closed by an eof (end of frame) pattern. all i ? code1 command frames consists of a start pulse followed by the data stream. the i ? code1 commands have a fix length and no eof is needed. these different phases of the transmit sequence may be monitored by watching modemstate of primarystatus- register (see 18.4.4). depending on the setting of bit txcrcen in the channelredundancy-register a crc is calculated and appended to the data stream. the crc is calculated according the settings in the channelredundancy register . 18.5.1.3 transmission of frames with more than 64 bytes to generate frames with more than 64 bytes, the -proc essor has to write data into the fifo buffer while the transmit command is active. the state machine checks the fifo status when it starts transmitting the last bit of the actual data stream (the check time is marked below with arrows). as long as the internal signal ?accept further data? is 1 further data may be loaded into the fifo. the cl rc632 appends this data to the data str eam transmitted via the rf-interface. if the internal signal ?accept further data? is 0 the tran smission will terminate. all data written into the fifo buffer after ?accept further data? went 0 will not be tr ansmitted anymore, but remain in the fifo buffer. fifo length fifo empty 0x01 0x00 txlastbits = 0 txlastbits bit0 bit7 bit0 bit7 txdata check fifo empty accept further data bit7 figure 18-5: timing for transmi tting byte oriented frames
philips semiconductors product s pecification rev. 3.0; may 2003 multiple protocol contactless reader ic cl rc632 126 confidential 18.5.2 receive command 16 hex command code hex action arguments and data returned data receive 16 activates receiver circuitry - data stream the receive-command activates the receiver circuitry. all data re ceived from the rf interface is returned via the fifo buffer. the receive-command can be started either by the - processor or automatically during execution of the transceive-command . note: this command may be used for test purposes only, since there is no timing relation to the transmit- command . 18.5.2.1 working with the receive command after starting the receive command the internal state machine decrements the value set in the rxwait- register with every bit-clock. from 3 down to 1 the anal og receiver circuitry is prepared and activated. when the counter reaches 0, the receiver starts monitoring the incoming signal at the rf-interface. if the signal strength reaches a level higher than the value set in the minlevel-register it finally starts decoding. the decoder stops, if no more signal can be detected on the receiver input pin rx. the decoder indicates termination of operation by setting bit rxirq . the different phases of the receive sequence ma y be monitored by watching modemstate of the primarystatus-register (see 18.4.4). note: since the counter values from 3 to 0 are necess ary to initialise the analog receiver circuitry the minimum value for rxwait is 3. 18.5.2.2 rf-channel redundancy and framing for iso 15693 the decoder expects a sof pattern at the beginning of each data stream. if a sof is detected, it activates the serial to parallel c onverter and gathers the incoming data bits. for i ? code1 the decoder do not expects a sof pattern at the beginning of eac h data stream. it activates the serial to parallel converter with the first received bit of the data. ever y completed byte is forwarded to the fifo. if an eof pattern (iso15693) is detected or the signal strength falls below minlevel set in the rxthreshold register , the receiver and the decoder stop, the idle-command is entered and an appropriate response for the - processor is generated (interrupt req uest activated, status flags set). if bit rxcrcen in the channelredundancy register is set a crc block is expected. the crc block may be one byte or two bytes according to bit crc8 in the channelredundancy register . remark: the received crc block is not forwarded to the fi fo buffer if it is corr ect. this is realised by shifting the incoming data bytes through an internal buffer of either one or two bytes (depending on the defined crc). the crc block remains in this internal buffer. as a consequence all data bytes are available in the fifo buffer one or two bytes delayed. if the crc fails all received bytes are forwarded to the fifo buffer (including the faulty crc itself).
philips semiconductors product s pecification rev. 3.0; may 2003 multiple protocol contactless reader ic cl rc632 127 confidential 18.5.2.3 collision detection if more than one label is within the rf-field during the label selection phase, they will respond simultaneously. the cl rc632 supports the al gorithm defined in iso 15693 as well as the i ? code1 anti- collision algorithm to resolve data-collisions of label serial numbers by doing the so-called anti-collision procedure. the basis for this is the ability to detect bit-collisions. bit-collision detection is supported by the used bit- coding scheme, namely the manchester-coding. if in the first and second half-bit of a bit a sub-carrier modulati on is detected, instead of forwarding a 1 or a 0 a bit collision will be signalled. to distinguish a 1 or 0-bit from a bit-collision, the cl rc632 uses the setting of colllevel . if the amplitude of the half-bit with smaller amplitude is larger than defined by colllevel , the cl rc632 indicates a bit-collision. if a bit-collision is detec ted, the error flag collerr is set. independent from the detected collision the receiver continues receiving t he incoming data stream. in case of a bit-collision, the decoder forwar ds 1 at the collision position. note: as an exception, if bit zeroaftercoll is set, all bits received after the first bit-collision are forced to zero, regardless whether a bit-collision or an unequivocal st ate has been detected. th is feature eases for the software to carry out the anti-colli sion procedure defined in iso 15693. when the first bit collision in a frame is detected, the bit position of this collision is stored in the collpos register . the collision position follows the table below: collision in bit value of collpos sof 0 lsbit of lsbyte 1 ? ? msbit of lsbyte 8 lsbit of second byte 9 ? ? msbit of second byte 16 lsbit of third byte 17 ? ? table 18-5: returned values for bit collision positions if a collision is detected in the sof a frame error is repor ted and no data is forwarde d to the fifo buffer. in this case the receiver continues to monitor the incomi ng signal and generates the correct notifications to the -processor when the ending of the faulty input stream is detected. this helps the -processor to determine the time when it is allowed next to send anything to the label.
philips semiconductors product s pecification rev. 3.0; may 2003 multiple protocol contactless reader ic cl rc632 128 confidential 18.5.2.4 communication errors the following table shows which event causes the setting of error flags: cause bit, that is set received data did not start with a sof pattern. framingerr the crc block is not equal the expected value. crcerr the received data is shorter than the crc block. crcerr a collision is detected. collerr table 18-6: communication error table 18.5.3 transceive command 1e hex command code hex action arguments and data returned data transceive 1e transmits data from fifo buffer to the label and then activates automatically the receiver data stream data stream the transceive-command first executes the transmit-command (see 18.4.1) and then automatically starts the receive-command (see 18.4.2). all data that shall be transmi tted is forwarded via the fifo buffer and all data received is returned via the fifo buffer. the transceive-command can be started only by the -processor. note: to adjust the timing relation between transmitting and receiving, the rxwait register is used to define the time delay from the last bit transmitted until the receiver is activated. furthermore, the bitphase register determines the phase-shift between the tr ansmitter and the receiver clock. 18.5.4 states of the label communication the actual state of the transmitter and re ceiver state machine can be fetched from modemstate in the primarystatus register . the assignment of modemstate to the internal action is shown in the following table: modemstate name of state description 000 idle neither the transmitter nor the receiver is in operation, since none of them is started or the transmitter has not got input data 001 txsof transmitting the ?start of frame? pattern 010 txdata transmitting data from the fi fo buffer (or redundancy check bits) 011 txeof transmitting the ?end of frame? pattern gotorx1 intermediate state passed, when receiver starts 100 gotorx2 intermediate state pass ed, when receiver finishes 101 preparerx waiting until the time period selected in the rxwait register has expired 110 awaitingrx receiver activated; awaiting an input signal at pin rx 111 receiving receiving data table 18-7: meaning of modemstate 18.5.5 state diagram for the label communication
philips semiconductors product s pecification rev. 3.0; may 2003 multiple protocol contactless reader ic cl rc632 129 confidential remark: i ? code1 do not have a sof and a eof gotorx1 (100) preparerx (101) awaitingrx (110) receiving (111) idle (000) c o m m a n d = r e c e i v e next bit clock frame received gotorx2 (100) rxwaitcounter = 0 signal strength > minlevel txsof (001) txdata (010) txeof (011) f i f o n o t e m p t y a n d c o m m a n d = ( t r a n s m i t or t r a n s c e i v e ) sof transmitted eof transmitted and command = transmit data transmitted eof transmitted and command = transceive set commandregister = idle (000) command = (transmit or receive or transceive) preparing to send the quit value rxmultiple = 1 && timeslotperiod > 0 && timeslot trigger && data in fifo idle (000) rxmultiple = 0 && timeslotperiod > 0 && timeslot trigger && data in fifo end of receive frame && rxmultiple = 0 && timeslotperiod = 0
philips semiconductors product s pecification rev. 3.0; may 2003 multiple protocol contactless reader ic cl rc632 130 confidential 18.6 commands to access the e2prom 18.6.1 writee2 command 01 hex 18.6.1.1 overview command code hex action arguments and data passed via fifo returned data via fifo writee2 01 get data from fifo buffer and write it to the e2prom start address lsb start address msb data byte stream - the writee2-command interprets the first two bytes in the fifo buffer as e2prom starting byte-address. any further bytes are interpreted as data bytes and are programmed into the e2prom, starting from the given e2prom starting byte-address. th is command does not return any data. the writee2-command can only be started by the -processor. it will not stop automatically but has to be stopped explicitly by the - processor by issuing the idle-command . 18.6.1.2 programming process one byte up to 16 byte can be programmed into t he eeprom in one programming cycle. the time needed will be in any case about 5.8ms. the state machine copies all data bytes prepared in the fifo buffer to the e2prom input buffer. the internal e2prom input buffer is 16 byte long, which is equal the block size of the e2prom. a programming cycle is started either if the last position of the e2prom input buffe r is written or if the last byte of the fifo buffer has been fetched. as long as there are unprocessed bytes in the fifo buffer or the e2prom programming cycle still is in progress, the flag e2ready is 0. if all data from the fifo buffer ar e programmed into the e2prom, the flag e2ready is set to1. together with the rising edge of e2ready the interrupt request flag txirq indicates a 1. this may be used to generate an interrupt when programming of all data is finished. after the e2ready bit is set to 1, the writee2-command may be stopped by the -processor by issuing the idle-command . note: during the e2prom programming indicated by e2ready = 0 the writee2 command cannot be stopped by any other command.
philips semiconductors product s pecification rev. 3.0; may 2003 multiple protocol contactless reader ic cl rc632 131 confidential 18.6.1.3 timing diagram the following diagram shows programming of 5 bytes into the e2prom: explanation: it is assumed, that the cl rc632 finds and reads byte 0 before the -processor is able to write byte 1 (t prog,del = 300 ns). this causes the cl rc632 to start the programming cycle, which needs about t prog = 5.8 ms. in the meantime the -processor stores byte 1 to byte 4 to the fifo buffer. assuming, that the e2prom starting byte-address is e.g. 16c hex then byte 0 is stored exactly there. the cl rc632 copies the following data bytes into the e2prom input buffer. copyi ng byte 3, it detects, that this data byte has to be programmed at the e2prom byte-address 16f hex . since this is the end of the memory block, the cl rc632 automatically starts a programming cycle. in the next turn, byte 4 will be programmed at the e2prom byte- address 170 hex . since this is the last data byte, the flags ( e2ready and txirq ) that indicate the end of the e2prom programming activity will be set. although all data has been programmed into the e2prom, the cl rc632 stays in the writee2-command . writing further data to the fifo would lead to furt her e2prom programming, continuing at the e2prom byte-address 171 hex . the command is stopped using the idle-command . 18.6.1.4 error flags for the writee2 command programming is inhibited for the e2prom blocks 0 (e2prom?s byte-address 00 hex to 0f hex ). programming to these addresses sets the flag accesserr . no programming cycle is started. addresses above 1ff hex are taken modulo 200 hex (for the e2prom memory organisation, refer to chapter 6.). nwrite data writee2 command active e2prom programming e2ready txirq write e2 adr lsb adr msb byte0 byte1 byte2 byte3 byte4 programming byte0 programming byte1, byte2, and byte3 programming byte4 t prog t prog t prog t prg,del idle cmd figure 18-7: timing diagram for e2prom programming
philips semiconductors product s pecification rev. 3.0; may 2003 multiple protocol contactless reader ic cl rc632 132 confidential 18.6.2 reade2 command 03 hex 18.6.2.1 overview command code hex action arguments returned data reade2 03 reads data from e2prom and puts it to the fifo buffer start address lsb start address msb number of data bytes data bytes the reade2-command interprets the first two bytes found in the fifo buffer as e2prom starting byte-address. the next byte specifies the num ber of data bytes that shall be returned. when all three argument-bytes are available in the fifo buffer, the specified number of data bytes is copied from the e2prom into the fifo buffer, starting from the given e2prom starting byte-address. the reade2-command can be triggered only by the -processor. it stops automatically when all data has been delivered. 18.6.2.2 error flags for the reade2 command reading is inhibited for the e2prom blocks 8 hex up to 1f hex ( key memory area). reading from these addresses sets the flag accesserr to 1. addresses above 1ff hex are taken modulo 200 hex (for the e2prom memory organisation, refer to chapter 6). 18.7 diverse commands 18.7.1 loadconfig command 07 hex 18.7.1.1 overview command code hex action arguments and data returned data loadconfig 07 reads data from e2prom and initialises the registers start address lsb start address msb - the loadconfig-command interprets the first two bytes found in the fifo buffer as e2prom starting byte-address. when the two argument-bytes are available in the fifo buffer, 32 bytes from the e2prom are copied into the cl rc632 control and configuration registers, starting at t he given e2prom starting byte-address. the loadconfig-command can only be started by the -processor. it stops automatically when all relevant registers have been copied.
philips semiconductors product s pecification rev. 3.0; may 2003 multiple protocol contactless reader ic cl rc632 133 confidential 18.7.1.2 register assignment the 32 bytes of e2prom content, beginning with the e2 prom starting byte-address , is written to the cl rc632 register 10 hex up to register 2f hex (for the e2prom memory organisation see also 6). note: the procedure for the register assignment is the same as it is for the start up initialisation (see 11.3). the difference is, that the e2prom starting byte-addre ss for the start up initialisation is fixed to 10 hex (block 1, byte 0). with the loadconfig-command it can be chosen. 18.7.1.3 relevant error flags for the loadconfig-command valid e2prom starting byte-addresses are in the range from 10 hex up to 60 hex . copying from block 8 hex up to 1f hex (keys) is inhibited. reading fr om these addresses sets the flag accesserr to 1. addresses above 1ff hex are taken modulo 200 hex (for the e2prom memory organisation refer to chapter 6). 18.7.2 calccrc command 12 hex 18.7.2.1 overview command code hex action arguments and data returned data calccrc 12 activates the crc-coprocessor data byte-stream - the calccrc-command takes all data from the fifo buffer as input bytes for the crc-coprocessor. all data stored in the fifo buffer before the command is started will be processed. this command does not return any data via the fifo buffer, but the co ntent of the crc-register can be read back via the crcresultlsb-register and the crcresultmsb-register . the calccrc-command can only be started by the -processor. it does not stop automatically but has to be stopped explicitly by the -processor with the idle-command . if the fifo buffer is empty, the calccrc-command waits for further input from the fifo buffer.
philips semiconductors product s pecification rev. 3.0; may 2003 multiple protocol contactless reader ic cl rc632 134 confidential 18.7.2.2 crc-copr ocessor settings for the crc-coprocessor the following parameters may be configured: parameter value bit register crc register length 8 bit or 16 bit crc crc8 channelredundancy crc algorithm algorithm according iso14443-a or according iso/iec3309 crc3309 channelredundancy crc preset value any crcpresetlsb, crcpresetmsb crcpresetlsb, crcpresetmsb table 18-8: crc-coprocessor parameters the crc polynomial for the 8-bit crc is fixed to 1 2 3 4 8 + + + + x x x x . the crc polynomial for the 16-bit crc is fixed to 1 5 12 16 + + + x x x . 18.7.2.3 status flags of the crc-coprocessor the status flag crcready indicates, that the crc- coprocessor has finished pr ocessing of all data bytes found in the fifo buffer. with the crcready flag setting to 1, an interrupt is requested with txirq being set. this supports interrupt driven usage of the crc-coprocessor. when crcready and txirq are set to 1, respectively, the content of the crcresultlsb- and crcresultmsb-register and the flag crcerr is valid. the crcresultlsb- and crcresultmsb-register hold the content of the crc register, the crcerr flag indicates crc validity for the processed data. 18.8 error handling during command execution if any error is detected during command executio n, this is shown by setting the status flag err in the primarystatus register . for information about the cause of the error, the -processor may evaluate the status flags in the errorflag register . error flag of the errorflag register related to command keyerr loadkeye2, loadkey accesserror writee2, reade2, loadconfig fifoovl no specific commands crcerr receive, transceive, calccrc framingerr receive, transceive parityerr receive, transceive collerr receive, transceive table 18-9: error flags overview
philips semiconductors product s pecification rev. 3.0; may 2003 multiple protocol contactless reader ic cl rc632 135 confidential 18.9 mifare ? classic security commands 18.9.1 loadkeye2 command 0b hex 18.9.1.1 overview command code hex action arguments and data returned data loadkeye2 0b reads a key from the e2prom and puts it into the internal key buffer start address lsb start address msb - the loadkeye2-command interprets the first two bytes found in the fifo buffer as e2prom starting byte-address. the e2prom bytes starting from the given starting byte-address are interpreted as key, stored in the correct key format as described in chapter 6. 4.1. when all two argument-bytes are available in the fifo buffer, the command execution starts. the loadkeye2-command can be started only by the - processor. it stops automatically after having copied the key from the e2prom into the key buffer. 18.9.1.2 relevant error flags for the loadkeye2-command if the key format is not correct (see chapter 6.4.1) an undefined value is copied into the key buffer and the flag keyerror is set. 18.9.2 loadkey command 19 hex 18.9.2.1 overview command code hex action arguments and data returned data loadkey 19 reads a key from the fifo buffer and puts it into the key buffer byte0 (lsb) byte1 ? byte10 byte11 (msb) - the loadkey-command interprets the first twelve bytes it finds in the fifo buffer as key, stored in the correct key format as described in chapter 6.4.1. when the twelve argument-bytes are available in the fifo buffer they are checked and, if valid, are copied into the key buffer (see also 19.2). the loadkey-command can only be started by the -processor. it stops automatically after having copied the key from the fifo buffer into the key buffer. 18.9.2.2 relevant error fl ags for the loadkey-command all bytes requested are copied from the fifo buffer to the key buffer. if the key format is not correct (see chapter 6.4.1) an undefined value is copied into the key buffer and the flag keyerror is set.
philips semiconductors product s pecification rev. 3.0; may 2003 multiple protocol contactless reader ic cl rc632 136 confidential 18.9.3 authent1 command 0c hex 18.9.3.1 overview command code hex action arguments and data returned data authent1 0c performs the first part of the crypto1 (mifare ? classic) card authentication card auth-command card block address card serial number lsb card serial number byte1 card serial number byte2 card serial number msb - the authent1-command is a special transceive-command : it takes six argument bytes which are sent to the card. the card?s response is not forwarded to the -pr ocessor, but is used to che ck the authenticity of the card and to prove authenticity of the cl rc632 to the card. the authent1-command can be triggered only by the -processor. the sequence of states for this command is the same as for the transceive-command (see 18.4.3). 18.9.4 authent2 command 14 hex 18.9.4.1 overview command code hex action arguments and data returned data authent2 14 performs the second part of the card authentication using t he crypto1 algorithm. - - the authent2-command is a special transceive-command. it does not need any argument byte but all necessary data which has to be sent to the card is as sembled by the cl rc632 itself. the card response is not forwarded to the -processor, but is used to ch eck the authenticity of the card and to prove authenticity of the cl rc632 to the card. the authent2-command can only be started by the -processor. the logical sequence for this command is the same as for the tran sceive-command (see 18.4.3). 18.9.4.2 effect of the authent2-command if the authent2-command was successful, authenticity of card and cl rc632 is proved. in this case, the control bit crypto1on is set automatically. when bit crypto1on is set, all further card communication is done encrypted, using the crypto1 security algorithm. if the authent2-command fails, bit crypto1on is cleared. note: the flag crypto1on can not be set by the -processor but only through a successfully performed authent2-command . the -processor may clear the bit crypto1on to continue with plain card communication. note: the authent2-command has to be executed immediately after a successful authent1-command (see 18.9.3). furthermore, the keys stored in the ke y buffer and those on the card have to match.
philips semiconductors product s pecification rev. 3.0; may 2003 multiple protocol contactless reader ic cl rc632 137 confidential 19 mifare ? classic authentication and crypto1 19.1 general the security algorithm implemented in mifare ? classic products is called crypto1. it is based on a proprietary stream cipher with a key leng th of 48 bits. to access data of a mifare ? classic card, the knowledge of the according key is necessary. for su ccessful card authentication and subsequent access to the card?s data stored in the eeprom, the correct key has to be available in the cl rc632. after a card is selected as defined in iso14443a the user may continue with the mifare ? classic protocol. in this case it is mandatory to perform a card authentication. the cr ypto1 authentication is a 3-pass authentication. this procedure is done automatically with the execution of authent1- (see 18.9.3) and the authent2-commands (see 18.9.4). during the card authentication proced ure, the security algorithm is initialised. the communication with a mifare ? classic card following a succes sful authentication is encrypted. 19.2 crypto1 key handling during the authentication command the cl rc632 reads the key from the internal key buffer. the key is always taken from the key buffer. therefore, t he commands for crypto1 authentication do not require addressing of a key. the user has to ensure, that t he correct key is prepared in the key buffer before the card authentication is triggered. the key buffer can be loaded ? from the e2prom with the loadkeye2-command (see 18.9.1) ? directly from the -processor via the fifo-buffer with the loadkey-command (see 18.9.2) this is shown in the following figure: fifo e2prom: keys key buffer crypto1 module writee2 serial data stream in (plain) serial data stream out (encrypted) during authent1 from the controller loadkey loadkeye2 . figure 19-1: key handling: block diagram
philips semiconductors product s pecification rev. 3.0; may 2003 multiple protocol contactless reader ic cl rc632 138 confidential 19.3 performing mifare ? classic authentication to enable authentication of mifare ? classic cards the crypto1 security algorithm is implemented. to obtain valid authentication, the correct key has to be available in the key buffer of the cl rc632. step 1: load the internal key buffer by means of the loadkeye2- (see 18.9.1) or the loadkey-command (see 18.9.2). step 2: start the authent1-command (see 18.9.3). when finished, chec k the error flags to obtain the status of the command execution. step 3: start the authent2-command (see 18.9.4). when finished, check the error flags and bit crypto1on to obtain the status of the command execution.
philips semiconductors product s pecification rev. 3.0; may 2003 multiple protocol contactless reader ic cl rc632 139 confidential 20 typical application 20.1 circuit diagram the figure below shows a typical application, where t he antenna is directly connected to the cl rc632: cl rc632 -processor bus processor control lines data bus irq rstpd dvdd avdd tvdd irq dvss avss oscin oscout 15 pf 15 pf 13.56 mhz dvdd avdd tvdd reset l0 l0 c0 c0 c2a c2b c1 tx1 tx2 tvss rx vmid c1 r1 r2 c4 100 nf c3 figure 20-1: circuit diagram for applic ation example: direct matched antenna
philips semiconductors product s pecification rev. 3.0; may 2003 multiple protocol contactless reader ic cl rc632 140 confidential 20.2 circuit description the matching circuit consists of an emc low pass filter (l0 and c0), a matching circuitry (c1 and c2), and a receiving circuit (r1, r2, c3 and c4), and the antenna itself. for more detailed information about designing and tuning an antenna please refer to the application note ?mifare ? and i code micore reader ic family; directly matched antenna design? and ?mifare ? (14443a) 13,56 mhz rfid proximity antennas? . 20.2.1 emc low pass filter the mifare ? system operates at a frequen cy of 13.56 mhz. this frequency is generated by a quartz oscillator to clock the cl rc632 and is also the basi s for driving the antenna with the 13.56 mhz energy carrier. this will not only cause emitted power at 13 .56 mhz but will also emit power at higher harmonics. the international emc regulations define the amplitude of the emitted power in a broad frequency range. thus, an appropriate filtering of the output si gnal is necessary to fulfil these regulations. a multi-layer board it is recommended to implement a low pass filter as shown in the circuit above. the low pass filter consists of the components l0 and c0 . the recommended values are given in the above mentioned application notes. note: to achieve best performance all components shall have at least the quality of the recommended ones. note: the layout has a major influence on the overall performance of the filter. 20.2.2 antenna matching due to the impedance transformation of the given low pass filter, the antenna coil has to be matched to a certain impedance. the matching elements c1 and c2 can be estimated and have to be fine tuned depending on the design of the antenna coil. the correct impedance matching is important to provi de the optimum performance. the overall quality factor has to be considered to guarantee a proper iso14443 communication scheme. environmental influences have to considered as well as common emc design rules. for details refer to the above mentioned application notes. note: do not exceed the current limits i tvdd , otherwise the chip might be destroyed. note: the overall 13.56mhz rfid proximity antenna design wi th the cl rc632 chip is straight forward and doesn?t require a special rf-know how. however, a ll relevant parameters have to be considered to guarantee an overall optimum performance toget her with international emc compliance.
philips semiconductors product s pecification rev. 3.0; may 2003 multiple protocol contactless reader ic cl rc632 141 confidential 20.2.3 receiving circuit the internal receiving concept of the cl rc632 make s use of both side-bands of the sub-carrier load modulation of the card response. no external filtering is required. it is recommended to use the internally generated vmid potential as the input potential of pin rx. this dc voltage level of vmid has to be coupled to the rx-pin via r2. to provide a stable dc reference voltage a capacitance c4 has to be connected between vmid and ground. considering the (ac) voltage limits at the rx-pin the ac voltage divider of r1 + c3 and r2 has to be designed. depending on the antenna coil design and the impedance matching the voltage at the antenna coil varies from antenna design to antenna design. ther efore the recommended way to design the receiving circuit is to use the given values for r1, r2, and c3 from the above mentioned application note, and adjust the voltage at the rx-pin by vary ing r1 within the given limits. note: r2 is ac-wise connected to ground (via c4). 20.2.4 antenna coil the precise calculation of the antenna coils? indu ctance is not practicable but the inductance can be estimated using the following formula. we recommend designing an antenna either with a circular or rectangular shape. lnh lcm l d kn 11 1 1 1 18 2 [] []ln , =? ? ? ? ? ? ? ? ? ? ? ? ? ? ? l 1 ............... length of one turn of the conductor loop d 1 ............. diameter of the wire or width of the pcb conductor respectively k............... antenna shape fact or (k = 1,07 for circular antennas and k = 1,47 for square antennas) n 1 ............. number of turns ln .............. natural logarithm function the actual values of the antenna inductance, resistance, and capacitance at 13.56 mhz depend on various parameters like: ? antenna construction (type of pcb) ? thickness of conductor ? distance between the windings ? shielding layer ? metal or ferrite in the near environment therefore a measurement of those parameters under re al life conditions, or at least a rough measurement and a tuning procedure is recommended to guarantee the optimum performance. for details refer to the above mentioned application notes.
philips semiconductors product s pecification rev. 3.0; may 2003 multiple protocol contactless reader ic cl rc632 142 confidential 21 test signals 21.1 general the cl rc632 allows different kind of signal measur ements. these measurements can be used to check the internally generated and received signals using the possi bilities of the serial signal switch as described in chapter 15. furthermore, with the cl rc632 the user may select internal analogue signals to measure them at pin aux and internal digital signals to observe them on pin mf out by register selections. these measurements can be helpful during the design-in phase to optimise the receiver?s behaviour or for test purpose. 21.2 measurements using the serial signal switch using the serial signal switch at pin mfout the user may observe data send to the card or data received from the card. the following tables give an overview of the different signals available. signaltomfout mfoutselect signal routed to mfout pin 0 0 low 0 1 high 0 2 envelope 0 3 transmit nrz 0 4 manchester with subcarrier 0 5 manchester 0 6 rfu 0 7 rfu 1 x digital test signal table 21-1 signal routed to mfout pin note: the routing of the manchester and the manchest er with subcarrier signal to the mfout is only possible at 106 kbaud according to iso14443a.
philips semiconductors product s pecification rev. 3.0; may 2003 multiple protocol contactless reader ic cl rc632 143 confidential 21.2.1 tx-control the following plot shows as an example an iso14443 a related communication. the signal measured at mfout using the serial signal sw itch to control the data sent to the card .setting the flag mfoutselect to 3 data sent to the card is shown nrz coded. mfoutselect set to 2 shows the miller coded signal. the rfout signal is measured directly on the antenna showing the pulse shape of the rf signal. for detail information concerning the pulse of the rf signal please refer to the application note ?mifare? design of mf rc 500 matching circuits and antennas? mfoutselect =3 serial data stream 2v/div. mfoutselect =2 serial data stream 2v/div. rfout 1v/div. figure 21 tx control signals
philips semiconductors product s pecification rev. 3.0; may 2003 multiple protocol contactless reader ic cl rc632 144 confidential 21.2.2 rx-control the following plot shows as an example an iso14443 a related communication. the following plot shows the beginning of a cards answer to a request signal. the signal rf shows the rf voltage measured directly on the antenna so t hat the cards load modulation is visible. mfoutselect set to 4 shows the manchester decod ed signal with subcarrier. mfoutselect set to 5 shows the manchester decoded signal. mfoutselect =5 manchester 2v/div. mfoutselect =4 manchester with subcarrier 2v/div. rf 1v/div. figure 22 rx control signals
philips semiconductors product s pecification rev. 3.0; may 2003 multiple protocol contactless reader ic cl rc632 145 confidential 21.3 analog test-signals the analog test signals may be routed to pin aux by selecting them with the register bits testanaoutsel . value signal name description 0 v mid voltage at internal node vmid 1 v bandgap internal reference voltage generated by the band gap. 2 v rxfolli output signal from the demodulator using the i-clock. 3 v rxfollq output signal from the de modulator using the q-clock. 4 v rxampi i-channel subcarrier signal amplified and filtered. 5 v rxampq q-channel subcarrier signal amplified and filtered. 6 v corrni output signal of n-channel correlat or fed by the i-channel subcarrier signal. 7 v corrnq output signal of n-channel correlat or fed by the q-channel subcarrier signal. 8 v corrdi output signal of d-channel correlat or fed by the i-channel subcarrier signal. 9 v corrdq output signal of d-channel correlat or fed by the q-channel subcarrier signal. a v evall evaluation signal from the left half bit. b v evalr evaluation signal from the right half bit. c v temp temperature voltage derived from band gap. d rfu reserved for future use e rfu reserved for future use f rfu reserved for future use table 21-2: analog test signal selection
philips semiconductors product s pecification rev. 3.0; may 2003 multiple protocol contactless reader ic cl rc632 146 confidential 21.4 digital test-signals digital test signals may be routed to pin mfout by setting bit signaltomfout to 1. a digital test signal may be selected via the register bits testdigisignalsel in register testdigiselect . the signals selected by a certain testdigisignalsel setting is shown in the table below: testdigisignalsel signal name description f4 hex s_data data received from the card. e4 hex s_valid shows with 1, that the signals s_data and s_coll are valid. d4 hex s_coll shows with 1, that a collis ion has been detected in the current bit. c4 hex s_clock internal serial clock: during transmission, this is the coder-clock and during reception this is the receiver clock. b5 hex rd_sync internal synchronised read signal (derived from the parallel -processor interface). a5 hex wr_sync internal synchronised write signal ( derived from the parallel -processor interface). 96 hex int_clock internal 13.56 mhz clock. 83 hex bpsk_out bpsk signal output e2 hex bpsk_sig bpsk signal?s amplitude detected 00 hex no test signal output as defined by mfoutselect are routed to pin mfout. table 21-3: digital test signal selection if no test signals are used, the value for the testdigiselect-register shall be 00 hex . note: all other values of testdigisignalsel are for production test purposes only.
philips semiconductors product s pecification rev. 3.0; may 2003 multiple protocol contactless reader ic cl rc632 147 confidential 21.5 examples of iso14443a anal og- and digital test signals fig. 22 shows a mifare ? classic card?s answer to a request command using the qclock receiving path. rx ?reference is given to show the manchester modula ted signal at the rx pin. this signal is demodulated and amplified in the receiver circuitry vrxampq show s the amplified side band signal having used the q- clock for demodulation. the signals vcorrdq and vc orrnq generated in the correlation circuitry are evaluated and digitised in the evaluation and digitize r circuitry. vevalr and vevall show the evaluation signal of the right and left half bit. finally, the digital test-signal s_data shows the received data which is send to the internal digital circuit and s_valid indicates that the received data stream is valid. figure 23. receiving path q-clock
philips semiconductors product s pecification rev. 3.0; may 2003 multiple protocol contactless reader ic cl rc632 148 confidential 21.6 examples of i ? code1 analog- and digital test signals fig. 17 shows the answer of an i ? code1 label ic to a unselected read command using the qclock receiving path. rx ?reference is given to show the manchester modula ted signal at the rx pin. this signal is demodulated and amplified in the receiver circuitry vrxampq show s the amplified side band signal having used the q- clock for demodulation. the signals vcorrdq and vc orrnq generated in the correlation circuitry are evaluated and digitised in the evaluation and digitize r circuitry. vevalr and vevall show the evaluation signal of the right and left half bit. finally, the digital test-signal s_data shows the received data which is send to the internal digital circuit and s_valid indicates that the received data stream is valid. vrxampq vcorrdq vcorrnq vevalr vevall sdata svalid receiving path q-clock 50 sec/dev. 500 sec/dev. figure 24. receiving path q-clock
philips semiconductors product s pecification rev. 3.0; may 2003 multiple protocol contactless reader ic cl rc632 149 confidential 22 electrical characteristics 22.1 absolute maximum ratings symbol parameter min max unit t amb,abs ambient or storage temperature range -40 +150 c dvdd avdd tvdd dc supply voltages -0.5 6 v v in,abs absolute voltage on any digita l pin to dvss -0.5 dvdd + 0.5 v v rx,abs absolute voltage on rx pin to avss -0.5 avdd + 0.5 v table 22-1: absolute maximum ratings 22.2 operating condition range symbol parameter conditions min typ max unit t amb ambient temperature - -25 +25 +85 c 3.0 3.3 3.6 v dvdd digital supply voltage dvss = avss = tvss = 0v 4.5 5.0 5.5 v avdd analog supply volt age dvss = avss = tvss = 0v 4.5 5.0 5.5 v tvdd transmitter supply voltage dvss = avss = tvss = 0v 3.0 5.0 5.5 v table 22-2: operating condition range 22.3 current consumption symbol parameter conditions min typ max unit idle command 6 9 ma stand by mode 3 5 ma soft power down mode 800 1000 a i dvdd digital supply current hard power down mode 1 10 a idle command, receiver on 25 40 ma idle command, receiver off 8 12 ma stand by mode 6.5 9 ma soft power down mode 1 10 a i avdd analog supply current hard power down mode 1 10 a continuous wave 150 ma tx1 and tx2 unconnected tx1rfen , tx2rfen = 1 4.5 6 ma i tvdd transmitter supply current tx1 and tx2 unconnected tx1rfen , tx2rfen = 0 65 130 a table 22-3: current consumption
philips semiconductors product s pecification rev. 3.0; may 2003 multiple protocol contactless reader ic cl rc632 150 confidential 22.4 pin characteristics 22.4.1 input pin characteristics pins d0 to d7, a0, and a1 have ttl input characteri stics and behave as defined in the following table. symbol parameter conditions min max unit i leak input leakage current -1.0 +1.0 a cmos: dvdd < 3.6 v 0.35 dvdd 0.65 dvdd v v t threshold ttl: 4.5 < dvdd 0.8 2.0 v table 22-4: standard input pin characteristics the digital input pins ncs, nwr, nrd, ale, a2, an d mfin have schmitt-trigger characteristics, and behave as defined in the following table. symbol parameter conditions min max unit i leak input leakage current -1.0 +1.0 a ttl: 4.5 < dvdd 1.4 2.0 v v t+ positive-going threshold cmos: dvdd < 3.6 v 0.65 dvdd 0.75 dvdd v ttl: 4.5 < dvdd 0.8 1.3 v v t- negative-going threshold cmos: dvdd < 3.6 v 0.25 dvdd 0.4 dvdd v table 22-5: schmitt-trigger input pin characteristics pin rstpd has schmitt-trigger cmos ch aracteristics. in addition, it is internally filtered with an rc-low- pass filter, which causes a relevant propagation delay for the reset signal: symbol parameter conditions min max unit i leak input leakage current -1.0 +1.0 a v t+ positive-going threshold cmos: dvdd < 3.6 v 0.65 dvdd 0.75 dvdd v v t- negative-going threshold cmos: dvdd < 3.6 v 0.25 dvdd 0.4 dvdd v t rstpd,p propagation delay 20 s table 22-6: rstpd input pin characteristics the analog input pin rx has the following input capacitance: symbol parameter conditions min max unit c rx input capacitance 15 pf table 22-7: rx input capacitance the analog input pin rx has the following input voltage range: symbol parameter conditions min max unit vi n,rx dynamical voltage input range avdd=5v, t=25c 1,1v 4,4 v table 22 -8 : rx input voltage range
philips semiconductors product s pecification rev. 3.0; may 2003 multiple protocol contactless reader ic cl rc632 151 confidential 22.4.2 digital output pin characteristics pins d0 to d7, mfout and irq have cmos output c haracteristics and behave as defined in the following table. symbol parameter conditions min typ max unit dvdd = 5 v, i oh = -1 ma 2.4 4.9 v v oh output voltage high dvdd = 5 v, i oh = -10 ma 2.4 4.2 v dvdd = 5 v, i ol = 1 ma 25 400 mv v ol output voltage low dvdd = 5 v, i ol = 10 ma 250 400 mv i o output current source or sink dvdd = 5 v 10 ma table 22-8: digital output pin characteristics note: irq pin may also be configured as open co llector. in that case the values for v oh do not apply. 22.4.3 antenna driver outp ut pin characteristics the source conductance of the antenna driver pins tx1 and tx2 for driving the high level can be configured via gscfgcw in the cwconductance register , while their source conductance for driving the low level is constant. for the default configuratio n, the output characteristic is specified below: symbol parameter conditions min typ max unit tvdd = 5.0 v, i ol = 20 ma 4.97 v v oh output voltage high tvdd = 5.0 v, i ol = 100 ma 4.85 v tvdd = 5.0 v, i ol = 20 ma 30 mv v ol output voltage low tvdd = 5.0 v, i ol = 100 ma 150 mv i tx transmitter output current continuous wave 200 ma peak table 22-9: antenna driver output pin characteristics
philips semiconductors product s pecification rev. 3.0; may 2003 multiple protocol contactless reader ic cl rc632 152 confidential 22.5 ac electrical characteristics 22.5.1 ac symbols each timing symbol has five characters. the first char acter is always 't' for time. the other characters indicate the name of a signal or the logic state of that signal (depending on position): designation: signal: designation: logic level: a address h high d data l low w nwr or nwait z high impedance r nrd or r/nw or nwrite x any level or data l ale or as v any valid signal or data c ncs n nss s nds or ndstrb and nastrb, sck example : t avll = time for address valid to ale low
philips semiconductors product s pecification rev. 3.0; may 2003 multiple protocol contactless reader ic cl rc632 153 confidential 22.5.2 ac operating specification 22.5.2.1 bus timing for s eparated read/write strobe symbol parameter min max unit t lhll ale pulse width 20 ns t avll multiplexed address bus valid to ale low (address set up time) 15 ns t llax multiplexed address bus valid after ale low (address hold time) 8 ns t llwl ale low to nwr, nrd low 15 ns t clwl ncs low to nrd, nwr low 0 ns t whch nrd, nwr high to ncs high 0 ns t rldv nrd low to data valid 65 ns t rhdz nrd high to data high impedance 20 ns t wldv nwr low to data valid 35 ns t whdx data hold after nwr high (data hold time) 8 ns t wlwh nrd, nwr pulse width 65 ns t avwl separated address bus valid to nrd, nwr low (set up time) 30 ns t whax separated address bus valid after nwr high (hold time) 8 ns t whwl period between sequenced read / write accesses 150 ns table 22-10: timing specification for separated read/write strobe note: for separated address and data bus the signal ale is not relevant and the multiple xed addresses on the data bus don?t care. for the multiplexed address and data bus the address lines a0 to a2 have to be connected as described in 4.3. t avll ale t lhll ncs t clwl t whdx t rhdz d0 ... d7 d0 ... d7 t wldv t rldv t llax t whwl nwr nrd t wlwh t llwl t whwl a0 ... a2 t avwl multiplexed addressbus a0 ... a2 t whax separated addressbus a0 ... a2 t whch figure 22-1: timing diagram fo r separated read/write strobe
philips semiconductors product s pecification rev. 3.0; may 2003 multiple protocol contactless reader ic cl rc632 154 confidential 22.5.2.2 bus timing for common read/write strobe symbol parameter min max unit t lhll as pulse width 20 ns t avll multiplexed address bus valid to as low (address set up time) 15 ns t llax multiplexed address bus valid after as low (address hold time) 8 ns t llsl as low to nds low 15 ns t clsl ncs low to nds low 0 ns t shch nds high to ncs high 0 ns t sldv,r nds low to data valid (for read cycle) 65 ns t shdz nds low to data high impedance (read cycle) 20 ns t sldv,w nds low to data valid (for write cycle) 35 ns t shdx data hold after nds high (write cycle, hold time) 8 ns t shrx r/nw hold after nds high 8 ns t slsh nds pulse width 65 ns t avsl separated address bus valid to nds low (hold time) 30 ns t shax separated address bus valid after nds high (set up time) 8 ns t shsl period between sequenced read/write accesses 150 ns t rvsl r/nw valid to nds low 8 ns table 22-11: timing specification for common read/write strobe note: for separated address and data bus the signal ale is not relevant and the multiplexed addresses on the data bus don?t care. for the multiplexed address and data bus the address lines a0 to a2 have to be connected as described in 4.3. t avll ale t lhll ncs t clsl t shdx t shdz d0 ... d7 d0 ... d7 t sldv,r t sldv,w t llax t shsl nds t slsh t llsl t shsl a0 ... a2 t avsl multiplexed addressbus a0 ... a2 t shax separated addressbus a0 ... a2 t rvsl r/nw t shch t shrx fi g ure 2 2 - 2 : timin g dia g ram for common read/write strobe
philips semiconductors product s pecification rev. 3.0; may 2003 multiple protocol contactless reader ic cl rc632 155 confidential 22.5.2.3 bus timing for epp symbol parameter min max unit t lllh nastrb pulse width 20 ns t avlh multiplexed address bus valid to nastrb high (set up time) 15 ns t lhax multiplexed address bus valid after nastrb high (hold time) 8 ns t clsl ncs low to ndstrb low 0 ns t shch ndstrb high to ncs high 0 ns t sldv,r ndstrb low to data valid (read cycle) 65 ns t shdz ndstrb low to data high impedance (read cycle) 20 ns t sldv,w ndstrb low to data valid (write cycle, set up time) 35 ns t shdx data hold after ndstrb high (write cycle, hold time) 8 ns t shrx nwrite hold after ndstrb high 8 ns t slsh ndstrb pulse width 65 ns t rvsl nwrite valid to ndstrb low 8 ns t slwh ndstrb low to nwait high 75 ns t shwl ndstrb high to nwait low 75 ns table 22-12: timing specification for common read/write strobe remark: the figure does not distinguish between the addres s write cycle and a data write cycle. take in account, that timings for the address write and da ta write cycle are different. for the epp-mode the address lines a0 to a2 have to be connected as described in 4.3. ncs t clsl t shdx t shdz d0 ... d7 d0 ... d7 a0 ... a7 t sldv,r t sldv,w ndstrb nastrb t slsh nwrite nwait t slwh t shwl t rvsl t shrx t shch figure 22-3: timing diagram for common read/write strobe
philips semiconductors product s pecification rev. 3.0; may 2003 multiple protocol contactless reader ic cl rc632 156 confidential 22.5.2.4 timing for spi compatible interface symbol parameter min max unit t sckl sck low pulse width 100 ns t sckh sck high pulse width 100 ns t shdx sck high to data changes 20 ns t dxsh data changes to sck high 20 ns t sldx sck low to data changes 15 ns t slnh sck low to nss high 20 ns table 22-13 timing specification for spi note: to send more than bytes in one datastream the nss signal has to low all the time. to send more than one datastream nss has to be se t to high level in between the datastreams. sck mosi nss miso t sckl t sckl t sckh t shdx t dxsh msb lsb msb lsb t sldx t dxsh t slnh figure 22 timing diagram for spi
philips semiconductors product s pecification rev. 3.0; may 2003 multiple protocol contactless reader ic cl rc632 157 confidential 22.5.3 clock frequency the clock input is pin 1, oscin. parameter symbol min typ max unit clock frequency (checked by the clock filter) f oscin 13.56 mhz duty cycle of clock frequency d fec 40 50 60 % jitter of clock edges t jitter 10 ps the clock applied to the cl rc632 acts as time basi s for the coder and decoder of the synchronous system. therefore stability of clock frequency is an important factor for proper performance. to obtain highest performance, clock jitter shall be as small as possible. this is best achieved usin g the internal oscillator buffer with the recommended circuitry (see 12).
philips semiconductors product s pecification rev. 3.0; may 2003 multiple protocol contactless reader ic cl rc632 158 confidential 23 e2prom characteristics the e2prom has a size of 32x16x8 = 4.096 bit. symbol parameter conditions min max unit t eeendurance data endurance 100.000 erase/write cycles t eeretention data retention t amb 55c 10 years t eeerase erase time 2.9 ms t eewrite write time 2.9 ms table 23-1:e2prom characteristics
philips semiconductors product s pecification rev. 3.0; may 2003 multiple protocol contactless reader ic cl rc632 159 confidential 24 esd specification to ensure the usage of the cl rc632 during producti on the ics is specified as described in the following table. test name conditions max esdh esd susceptibility (human body model) 1500 ? , 100 pf 1 kv esdm esd susceptibility (machine model) 0.75 h, 200 pf 100 v table 24-1. esd specification
philips semiconductors product s pecification rev. 3.0; may 2003 multiple protocol contactless reader ic cl rc632 160 confidential 25 package outlines 25.1 so32 unit a max. a 1 a 2 a 3 b p cd (1) e (1) eh e ll p qz y w v references outline version european projection issue date iec jedec eiaj mm inches 2.65 0.10 0.25 0.01 1.4 0.055 0.3 0.1 2.45 2.25 0.49 0.36 0.27 0.18 20.7 20.3 7.6 7.4 1.27 10.65 10.00 1.2 1.0 0.95 0.55 8 0 o o 0.25 0.1 0.004 0.25 dimensions (inch dimensions are derived from the original mm dimensions) note 1. plastic or metal protrusions of 0.15 mm maximum per side are not included. 1.1 0.4 sot287-1 (1) 0.012 0.004 0.096 0.086 0.02 0.01 0.050 0.047 0.039 0.419 0.394 0.30 0.29 0.81 0.80 0.011 0.007 0.037 0.022 0.01 0.01 0.043 0.016 w m b p d h e z e c v m a x a y 32 17 16 1 a a 1 a 2 l p q detail x l (a ) 3 e pin 1 index 0 5 10 mm scale so32: plastic small outline package; 32 leads; body width 7.5 mm sot287-1 95-01-25 97-05-22 figure 255-1: outline and dimension of cl rc632 in so32
philips semiconductors product s pecification rev. 3.0; may 2003 multiple protocol contactless reader ic cl rc632 161 confidential definitions data sheet status objective specification this data sheet contains target or goal specifications for product development. preliminary specification this data sheet contains preliminary data; supplementary data may be published later. product specification this data sheet contains final product specifications. limiting values limiting values given are in accordance with the absolute maximum rating system (iec 134). stress above one or more of the limiting values may cause permanent damage to the device. these are stress ratings only and operation of the device at these or at any other conditions above those given in the characteristics section of the specification is not implied. exposure to limiting values for extended periods may affect device reliability. application information where application information is given, it is adv isory and does not form part of the specification. 26 disclaimers 26.1 life support applications these products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. philips customers using or selling these products for use in such applications do so on their own risk and agree to fully indemnify philips for any damages resulting from such improper use or sale. 26.2 licence policy purchase of this philips ic with a functionally ac cording to iso/iec 15693 standard does not convey an implied license under any patent right on this standar d. a license for the philips portfolio of patents on the iso/iec 15693 standard can be obtained via the philips intellectual property and standards department. for more information please contact the nearest philips semiconductors sales office.
27 revision history 27.1 update from revision 2.0 to revision 3.0 the whole document was editorial revised. new phras ings and additional descriptions have been added. the table below refers to relevant changes in content. chapter description 5.2.4.2 added bits 4- 3: ?iso selection? 22.4.1 chapter ?input pin characteristics?: dy namical input voltage range for rx pin added table 0-1: update from revision 2.0 to revision 3.0 27.2 versions up to revision 3.0 revision date cpcn page description 3.0 november2002 - first published version 2.0 june 2002 - second published version 1.0 january2002 - internal version table 0-2: document revision history
philips semiconductors - a worldwide company contact information for additional information please visit http://www.semiconductors.philips.com .fax: +31 40 27 24825 for sales offices addresses send e-mail to: sales.addresses@www.semico nductors.philips.com . ? koninklijke philips electronics n.v. 2002 sca74 all rights are reserved. reproduction in whole or in part is pr ohibited without the prior written consent of the copyright owne r. the information presented in this document does not form part of any quotation or contract, is believed to be accurate and reli able and may be changed without any notice. no liability will be accepted by the publis her for any consequence of its use. publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. p h i l i p s s e m i c o n d u c t o r s

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